International Business Machines Corporation

Ansys, Inc.

Emrah Acar

Rajiv V Joshi

Tong Li

Sani Richard Nassif

Scott Johnson

Joao Moreno Geada

Altan Odabasi

Luis Alfonso Lastras-Montano

Ying Liu

Michele M Franceschini

Ruchir Puri

Rajesh Ramkrishna Bordawekar

Livio B Soares

Haifeng Qian

Amith Singhee

Damir Anthony Jamsek

Aditya Bansal

Kanak Behari Agarwal

Alexander V Rylyakov

Yurii A Vlasov

William M Green

Jonathan E Proesel

Anirudh Devgan

Peter Feldmann

Bhavna Agrawal

Michael P Beakes

Gradus Janssen

Steven G Walker

Sudarsana Reddy Mallu

Tinu Thomas

Mirza Milan

Dureseti Chidambarrao

Alper Buyuktosunoglu

Pradip Bose

Michael Stephen Floyd

Gregory Scott Still

Rama Nand Singh

Bishop Chapman Brock

Liang-Teck Pang

Ivan L Wemple

Colin James Parris

Richard Daniel Kimmel

Maria Lorena Pesantez

Haihua Su

Ali Sadigh

Timothy S Lehner

Ravishankar Arunachalam

Qian Haifeng

Youlin Liao

Moyra K McManus

Matthew J Sullivan

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

DVD simulation using microcircuits

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.

Voltage drop analysis using local circuit representation

A computer-implemented method and computing system are provided for failure prediction of a batch of manufactured objects. The method includes classifying, by a processor sing a simulation, a set of samples with uniformly distributed parameter values, to generate sample classifications for the batch of manufactured objects. The method further includes determining, by the processor, a centroid of failing ones of the samples in the set, based on the sample classifications. The method also includes generating, by the processor, a new set of samples with a distribution around the centroid of the failing ones of the sample in the set. The method additionally includes populating, by the processor, a nearest neighbor vector space using the new set of samples. The method further includes classifying, by the processor, the new set of samples by performing a nearest neighbor search on the nearest neighbor vector space using a distance metric.

Predictive analytics for failure detection

A computer-implemented method and computing system are provided for failure prediction of a batch of manufactured objects. The method includes classifying, by a processor using a simulation, a set of samples with uniformly distributed parameter values, to generate sample classifications for the batch of manufactured objects. The method further includes determining, by the processor, a centroid of failing ones of the samples in the set, based on the sample classifications. The method also includes generating, by the processor, a new set of samples with a distribution around the centroid of the failing ones of the sample in the set. The method additionally includes populating, by the processor, a nearest neighbor vector space using the new set of samples. The method further includes classifying, by the processor, the new set of samples by performing a nearest neighbor search on the nearest neighbor vector space using a distance metric.

Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin. The group identifier and the time delay at each pin can limit the switching activities in the DVD simulations to reduce pessimistic results from the simulations. Other methods are described, and data processing systems and machine readable media that cause such systems to perform these methods are also described.

DVD analysis that accounts for delays

This disclosure describes methods, systems and media for analyzing voltage drops in a power delivery network in a simulated design of an electrical circuit. In one embodiment, a system determines, for a victim element ('victim'), a voltage drop caused by each aggressor element ('aggressor') in a set of aggressors in the design and creates a data structure that includes, for each victim, at least one of: (1) each voltage drop caused by each aggressor in the set of aggressors or (2) a sum of the voltage drops on the victim caused by all of the aggressors in the set of aggressors. The system can then compute a set of simulations based on random inputs to generate a distribution of possible voltage drops for each victim using data in the data structure.

Dynamic voltage drop analysis with improved coverage

Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.

Concept analysis operations utilizing accelerators

A system, method and computer program product for sorting Integrated Circuits (chips), particularly microprocessor chips, and particularly that predicts chip performance or power for sorting purposes. The system and method described herein uses a combination of performance-predicting parameters that are measured early in the process, and applies a unique method to project where the part, e.g., microprocessor IC, will eventually be sorted. Sorting includes classifying the IC product to a subset of a family of products with the product satisfying certain performance characteristics or specifications, in the early stages of manufacturing, e.g., before the end product is fully fabricated.

Power and performance sorting of microprocessors from first interconnect layer to wafer final test

In one example, a method for evaluating a system includes constructing a macro-model of the system comprising a multiple-order polynomial equation that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the macro-model.

Multi-dimension variable predictive modeling for yield analysis acceleration

Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.

Matrix ordering for cache efficiency in performing large sparse matrix operations

A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be statistically analyzed, performing a table look-up for individual components of the plurality of components, acquiring a result for the condition to be statistically analyzed based on information in a table when a component of the plurality of components is defined in the table, and designing a circuit from integrated circuits based on conducting the statistical analysis of the system. The designing the circuit from the integrated circuits is implemented in manufacturing the integrated circuits.

Efficient deployment of table lookup (TLU) in an enterprise-level scalable circuit simulation architecture

A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be statistically analyzed, a module that is configured to perform a table look-up for individual components of the plurality of components, and a module that is configured to acquire a result for the condition to be statistically analyzed based on information in a table in which a component of the plurality of components is defined. A result of the statistical analysis provides a design of the circuit for a fabrication facility for manufacturing integrated circuits.

A method and a system including a processor performing a failure region exploration through uniform sampling of plurality of variables related to a circuit, the processor shifting probability distributions to explore failure probability, the processor estimating the failure probability and standard deviation by determining mean and standard deviation of failure probability of a circuit, the processor terminating sampling when a confidence interval bounds converge, and a peripheral device providing a report on the failure of the circuit when the sampling is terminated by the processor.

Massive multi-dimensionality failure analytics with smart converged bounds

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Montvale, NJ, United States of America

Emrah Acar