Siemens Aktiengesellschaft

Infineon Technologies Ag

Carl Zeiss Microscopy Gmbh

Carl Zeiss Nts Gmbh

Other

Austria Wirtschaftsservice Gesellschaft MIT Beschrankter Haftung

Innovationsagentur Gesellschaft M.b.h.

Innovationsagentur Gesellschaft

Emmerich Bertagnolli

Bernd Goebel

Helmut Klose

Josef Willer

Wolfram Buehler

Heinz Wanzenboeck

Franz Hofmann

Holger Doemer

Barbara Hasler

Gottfried Hochleitner

Eve Marie Martin

Alexander Rosenthal

Daniel Fischer

Wolfgang Roesner

Paul-Werner Von Basse

Boris Mizaikoff

Carl Kuebler

Wolfram Buhler

Camille Stebler

Bernd Gobel

Heinz Wanzenbock

Alois Lugstein

Christine Kranz

Werner Weber

Hans Reisinger

Siegfried Schwarzl

Martin Kerber

Till Schl&ouml;sser

Markus Biebl

Holger Hubner

Ulrike Zeile

Andreas Vom Felde

Ulrich Naeher

Michael Bianco

Gustav Beckmann

Hermann Jacobs

Ludwig Treitinger

Siegmar Koppe

Holger Dömer

Wolfram Bühler

Matthias Lang

Joerg Stodolka

Peter Roediger

Karl-Heinz Tietgen

Herbert Kabza

Carl Kübler

Markus Fischer

Heinz Wanzenböck

A process of preparing a lamella from a substrate includes manufacturing a protection strip on an edge portion of the lamella to be prepared from the substrate, and preparing the lamella, wherein the manufacturing the protection strip includes a first phase of activating a surface area portion of the substrate, and a second phase of electron beam assisted deposition of the protective strip on the activated surface area portion from the gas phase.

Method of depositing protective structures

A processing system for processing an object () is provided, wherein the processing system is adapted, to focus a first energy beam, in particular an electron beam (), and a second energy beam, in particular an ion beam (), on a focusing region () in which a object () to be processed is arrangeable. A processing chamber wall () having two openings () for traversal of both energy beams and a connector () for supplying process gas delimits a processing chamber () from a vacuum chamber () of the processing system. Processing the object by activating the process gas through one of the energy beams and inspecting the object via one of the energy beams is enabled for different orientations of the object relative to a propagation direction of one of the energy beams.

Processing system

A particle beam systemfor cleaning itself comprises an irradiation system to direct electromagnetic radiation onto the surfaces to be cleaned and a supply systemto supply a precursor gas to the interior of the vacuum chamberof the particle beam system. The precursor gas is activated in a vicinity of the surfaces to be cleaned and is converted into a reaction gas which reacts with the contaminants present on the irradiated surfaces such that said contaminants may be pumped out then.

Particle beam microscopy system and method for operating the same

A processing system comprises a gas supply apparatus with which process gas is supplied to an object. An activation beam activates the gas thereby inducing a chemical reaction between material at the surface of the object and the process gas causing ablation of material from the surface or deposition of material at the surface. The gas supply apparatus is formed from a stack of plates providing a gas conduit system between at least one gas inlet and at least one gas outlet.

System for processing an object

A system and a method for processing and inspecting an object are provided, wherein the system comprises a particle beam column, an object holder and a gas supply apparatus. Thereby, the object holder is formed comprising a base, a first table displaceable relative to the base, a second table displaceable relative to the first table and a third table rotatable relative to the second table, wherein the cannula of the gas supply apparatus is fixed at the first table.

System and method for processing an object

The invention involves an array to couple a live cell, in particular a nerve cell, with an electronic circuit to pick up directly or indirectly electrically active cell signals and/or to electronically stimulate the cell, where the coupling array comprises a transistor (T) with a double gate, where one of the gates is designed as a control gate (CG) to select the transistor via external control signals, and the other gate (FG) is connected to an electrically conducting contact element () which may be brought into contact with the cell () to register changes in the electric properties of the cell.

Double gate transistor arrangement for receiving electrical signals from living cells

A method of producing a device for simultaneously carrying out an electrochemical and a topographical near field microscopy is disclosed, which is characterized in that a probe suitable for topographic near field microscopy is covered by a conductive material, the conductive material is covered by an insulating layer, and the conductive material and the insulating layer are removed in the region of the immediate tip of the probe.

Method for producing a device for simultaneously carrying out an electrochemical and a topographical near-field microscopy

A device for simultaneously carrying out an electro-chemical and a topographical near field microscopy is described, which device comprises a region for topographical near field measurement and a region for electrochemical near field measurement, with the region for topographical near field measurement extending completely as far as to the immediate tip of the arrangement, characterized in that the region for electrochemical near field measurement starts at a defined distance from the immediate tip.

Device for simultaneously carrying out an electrochemical and a topographical near-field microscopy

A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G. DRAMS, and method for fabricating such a capacitor

Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches. Above the recess, an insulating structure is preferably disposed in the first indentation and adjoins two adjacent ones of the insulation trenches.

DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties

A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor

An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F .

Integrated circuit having at least two vertical MOS transistors and method for manufacturing same

A method for fabricating a stacked capacitor in a semiconductor configuration, in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The semiconductor configuration having one electrode of a stacked capacitor produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. After the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed, with the result that the electrode has the same conductivity type as the terminal region and no pn junction occurs between the electrode and terminal region.

Method for fabricating a stacked capacitor in a semiconductor configuration, and stacked capacitor fabricated by this method

A storage cell is described which includes a storage element whose electric resistance represents an information unit and can be influenced by a magnetic field as well as a transistor which when the information is read out allows for the corresponding storage cell to be selected from among the storage cells. To write the information unit, a write line and a bit line are provided which intersect in the area of the storage element and are able to generate the magnetic field. The storage cell is disposed between the bit line and a shared voltage supply connection. The storage cell is disposed between the bit line and the write line and the write line can coincide with a gate line that controls the transistor. The transistor is a planar or vertical transistor. The storage element and the transistor can be positioned next to or on top of each other.

Memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and method for fabricating it

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Vienna, Austria

Emmerich Bertagnolli