Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics Gmbh

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Emmanuel Josse

Thomas Skotnicki

Denis Rideau

Olivier Nier

Pierre Morin

Stephane Monfray

Philippe Candelier

Francois Andrieu

Olivier Weber

Marios Barlas

Sonarith Chhun

Dominique Golanski

Gregory Bidal

Alexandre Dray

Jerome Mazurier

Thierry Devoivre

Elise Baylac

Sébastien Lefebvre

Kirill Shiianov

A phase change filter is formed by an arrangement of dots, wherein each dot is made of a phase change material. A heating layer of electrically conductive material extends under the arrangement of dots. Current passing through the heating layer changes the dots between two states to alter attenuation of light passing through the filter.

Planar cell nanoheater design and cell architecture for programmable phase change filters

A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

Method of manufacturing a device with MOS transistors

An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

Multi-orientation integrated cell, in particular input/output cell of an integrated circuit

The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Method of forming stressed semiconductor layer

One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Method of stressing a semiconductor layer

One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

Method of forming stressed SOI layer

A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer () of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Integrated electronic circuit incorporating a capacitor

The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portionresting on the flanks of the pillar and an isolated internal portionsituated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL,PLextending between the source and drain regions, and forming two very fine pillars.

Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor

The vertical transistor includes, on a semiconductor substrate, a vertical pillarhaving one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layersituated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first regionresting on the gate dielectric layerand a second regionfacing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavitiesS,D.

Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor

The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion resting on the flanks of the pillar and an isolated internal portion situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL , PL extending between the source and drain regions, and forming two very fine pillars.

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La Motte Servolex, France

Emmanuel Josse