International Business Machines Corporation

Infineon Technologies Ag

Emmanuel F Crabbe

Bernard S Meyerson

Johannes M Stork

Sophie Verdonckt-Vandebroek

Hans-Joachim Barth

David Louis Harame

Keith Aelwyn Jenkins

Henry Atkinson Nye, Iii

Douglas Wayne Kemerer

Joseph L Chan

Lloyd G Burrell

Gary L Patton

David K Anderson

Jeffrey L Snare

A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().

Support structures for wirebond regions of contact pads over low modulus materials

A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transconductance of the device can be optimized by controlling the location of the carriers within the channel.

Method of making graded channel effect transistor

Graded channel field effect transistor

A semiconductor chip having an on-chip ground plane comprising a low resistivity semiconductor region in a plurality of non-device regions of the chip and reach-through regions electrically connected to the low resistivity semiconductor region. One or more front-side contacts are used to electrically connect the reach-through regions and the low resistivity semiconductor region to a ground potential to electrically ground the on-chip ground plane.

On-chip ground plane for semiconductor devices to reduce parasitic

A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

Graded bandgap single-crystal emitter heterojunction bipolar transistor

Growing community of inventors

Chappaqua, NY, United States of America

Emmanuel F Crabbe