Texas Instruments Corporation

Emmanuel Ego

Gilbert Laurenti

Jean-Pierre Giacalone

Marc Couvrat

Douglas E Deao

Mark L Buser

Shigeshi Abiko

Eric L Badi

Armelle Laine

Herve Catan

Karim Djafarian

Vincent Gillet

Gael Clave

Alain Boyadjian

Anne Lombardot

Jean-Marc Philippe Bachot

Francois Theodorou

Yves Masse

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Laurent Ichard

Frederic Nidegger

David Russell

N M Ganesh

An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.

Bit field processor

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

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Antibes, France

Emmanuel Ego