Université De Bretagne Sud

Centre National De La Recherche Scientifique

Utah State University

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

University of Massachusetts

Technische Universitat Kaiserslautern

Creonic Gmbh

Centre National De La Recherche Scientifique-cnrs

Emmanuel Boutillon

Cédric Marchand

Laura Conde-Canencia

Hassan Harb

Chris Winstead

Oussama Abassi

Valentin Savin

Timo Lehnigk-Emden

Philipp Schläfer

Gopalakrishnan Sundararajan

Maciej Ciesielski

Serkan Askar

Ahmed Abdmouleh

Jeremie Guillot

Philipp SCHLÄFER

Franklin Cochachin Henostroza

Joseph Jabour

The invention relates to the transmission and reception of non-binary error correcting code words. The transmission method includes a first modulation () which implements a set of q sequences comprising q−1 sequences of q−1 chips, each sequence being obtained by circular shifting of a basic pseudo-random sequence, and a partially invariant sequence, invariant to a predetermined subset of circular shifts. The first modulation () further implements an association between each code word symbol and a sequence of the set of sequences wherein said finite field GFhas a non-zero primitive element, the symbol zero being associated with said partially invariant sequence and a symbol equal to a power j of the primitive element, j being an integer comprised between 0 and q−2, being associated with a pseudo-random sequence determined by j circular shifts of the basic pseudo-random sequence.

Methods and devices for transmitting and receiving non-binary error correcting code words

Embodiments of the invention provide an elementary check node processing unit () implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit () being linked to a variable node processing unit () and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit () comprises a calculation unit () which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit () also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit () also comprises a selection unit () which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit () then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit ().

Offset value determination in a check node processing unit for message-passing decoding of non-binary codes

Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises:

Variable node processing methods and devices for message-passing decoding of non-binary codes

Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to:

Simplified check node processing in non-binary LDPC decoder

A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.

Check node processing methods and devices with insertion sort

Embodiments of the invention provide a check node processing unit configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units to determine permuted variable node messages by applying permutations to at least three variable node messages generated by variable node processing units; a syndrome calculation unit to determine a set of syndromes comprising binary values from the permuted variable node messages; a decorrelation and permutation unit configured, for each check node message of a given index, to: determine a permuted index by applying the inverse of the one or more permutations; select at least one valid syndrome in the set of syndromes; and determine at least one candidate check node component; and a selection unit to determine at least one check node message from the candidate check node component.

Simplified, presorted, syndrome-based, extended min-sum (EMS) decoding of non-binary LDPC codes

A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.

Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes

Devices and methods for decoding a signal encoded using an error correcting code are provided. For example, a check node processing unit is provided for a decoder to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components. The check node processing unit comprises a data structure configured to store the input messages, the components of the input messages being associated with an integer index. The check node processing unit also comprises a data processing unit configured to apply one or more iterations of a transformation operation to at least a part of the data structure depending on at least some of the components of the input messages associated with a given value of the integer index, which provides a transformed data structure. The check node processing unit further comprises a calculation unit configured to determine at least one output message from the transformed data structure.

Methods and devices for error correcting codes decoding

At least a method and an apparatus are presented to decode a signal encoded using an error correcting code. For example, a decoder comprising a check node processing unit is presented. The check node processing unit is configured to receive at least three input messages and to generate at least one output message. A syndrome calculator is configured to determine a set of syndromes from the at least three input messages using at least two elementary check node processors. A decorrelation unit is configured to determine, in association with at least an output message, a set of candidate components from the set of syndromes. A selection unit is configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with the at least an output message.

Elementary check node processing for syndrome computation for non-binary LDPC codes decoding

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives dinput lists Uand delivers and delivers doutput lists V, with i&#x2208;[1 . . . d]. Each input list and output list includes nelements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q&#x3e;n. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of delements of input lists U. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.

Method for controlling a check node of a NB-LDPC decoder and corresponding check node

At least a method and an apparatus are presented for decoding a signal. For example, a decoder is presented for determining an estimate of an encoded signal. The decoder comprises one or more variable node processing units and one or more check node processing units configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with the symbol. The at least one check processing unit is further configured to calculate at two or more elementary check node processors a set of syndromes from at least three permuted messages, a syndrome comprising a binary vector; generate at least one check node message from the set of syndromes depending on the binary vector, and send the at least one check node message to a signal estimation unit.

Elementary check node-based syndrome decoding using pre-sorted inputs

At least a method and an apparatus are presented for determining a coded modulation scheme, the coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation, a modulation scheme, and a modulation mapping. Two or more candidate modulation mappings and two or more candidate parity-check equations are determined defining the at least one non-binary error correcting code, a candidate set comprising a candidate modulation mapping and at least one candidate parity-check equation providing codeword vectors and being associated with one or more metrics, each metric being evaluated for a number of distinct pairs of codeword vectors having an Euclidean distance of a defined value. One candidate modulation mapping and at least one candidate parity-check equation are selected according to an optimization criterion applied to the one or more metrics.

Methods and devices for generating optimized coded modulations

A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nFIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.

Decoding of non-binary LDPC codes

For decoding messages, a decoder exchanges single-bit messages for a data channel between a plurality of M parity nodes and a plurality of N symbol nodes. Each parity node has one or more adjacent symbol nodes with a plurality of edges between the parity node and each adjacent symbol node. An extrinsic decision and an extrinsic parity value are calculated based on a time-varying lookup table. The lookup table stores the locally maximum-likelihood extrinsic decision for a quantized number of data channel states as a function of adjacent extrinsic parity values.

Decoding low-density parity-check maximum-likelihood single-bit messages

For low complexity error correction, a decoder modifies each reliability metric of an input data stream with a random perturbation value. The reliability metric comprises a weighted sum of a channel measurement for the input data stream and parity check results for the input data stream. In addition, the decoder may generate an output data stream as a function of the reliability metrics.

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Emmanuel Boutillon