Broadcom Corporation

Argo Semiconductors Fs Ltd (he 359654)

Emmanouil Frantzeskakis

Georgios Sfikas

Henrik Tholstrup Jensen

Stephen Wu

Brima Babatunde Ibrahim

Radha Srinivasan

Ioannis Loukas Syllaios

Padmanava Sen

Konstantinos Vrysas

The present invention, a Digital Power Amplifier (DPA) with filtered output relates to the transmission circuitry of wireless communications systems and more particularly to high frequency power amplifier circuits using digital intensive techniques on cost efficient semiconductor technologies. Today, we experience an ever-increasing need for low cost, low power wireless transmitters in the millimeter wavelength region. Current solutions rely on analog PA circuits. The background art does not contain a solution for bridging the gap between the operation frequencies of the digital circuits on a cost-efficient technology such as CMOS and the millimeter wavelength transmission frequencies demanded in numerous applications. The DPA allowing the direct feeding of digital data to a high frequency amplifying circuit. In this way, design challenging and costly analog processing up-conversion stages are avoided. The DPA comprises a bank of switching amplifying elements, a switch capacitor trap filter taping on the bank of switching amplifying elements for shaping the frequency characteristic of the produced radio frequency (RF) waveform and an adaptive biasing circuit able of dynamically controlling the power consumption within the switching amplifying elements. It can have a wide spectrum of applications where low cost but high efficiency power amplifiers are needed, such as in the Internet of Things (IoT), Wi-Fi and 5G cellular communications.

Digital power amplifier with filtered output

Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Digital phase locked loop with feedback loops

The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.

Digital phase-locked loop with wide capture range, low phase noise, and reduced spurs

Digital phase locked loop circuits

Digital phase locked loop circuits with multiple digital feedback loops

The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.

Fractional-N phase locked loop based on bang-bang detector

Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wand Vfrom an input data signal Uand a feedback signal Y. The generated digital signals Wand Vcombined may carry the information content of Uwhile they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal W, which may be scaled appropriately in frequency, and the digital signal Vmay be provided as inputs to the PLL. The feedback signal Ymay be a digital signal that may correspond to the analog feedback signal Pthat may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wand Vfor properly transmitting the input data signal U.

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Ilioupolis, Greece

Emmanouil Frantzeskakis