Texas Instruments Corporation

Emily A Groves

Douglas E Paradis

Thomas Dyer Bonifield

James Carl Baker

Julie S England

Barry Lanier

Charles P Monaghan

Glenn A Cerny

Wayne Edward Bailey

Gary J Grant

Homer K Cheung

A method of forming a semiconductor device and the device, the method comprising the steps of providing a silicon substrate of predetermined conductivity type having a layer of silicon oxide with a first mask thereon, implanting a first impurity of the predetermined conductivity type into the substrate in unmasked regions of the substrate, masking the substrate except for a small region immediately adjacent the first mask with a second mask, implanting a second impurity of the predetermined conductivity type into the substrate in the unmasked regions of the substrate to cause some of the impurity to extend in the substrate beneath the first mask, removing the second mask, oxidizing the substrate with the first mask thereon to form a bird's beak extending beneath the first mask with the impurities extending along the bird's beak both beneath and external to the first mask and completing fabrication of a semiconductor device on substrate. The device is a semiconductor device having a silicon substrate of predetermined conductivity type with a semiconductor device structure therein, and a bird's beak region on the substrate wherein the substrate has a higher level of impurity of the predetermined conductivity type along and directly beneath the bird's beak region than in the bulk of the substrate.

Ion implant of the moat encroachment region of a LOCOS field isolation

A hybrid semiconductor device which comprises a semiconductor substrate having electrical devices therein with a plurality of spaced apart relatively rigid standoffs of electrically insulating material disposed over the substrate. Each of the standoffs has a substantially planar exposed surface remote from the substrate. A first layer of electrically insulating material more resilient than the standoffs is disposed over the substrate and between the standoffs and has an upper surface coplanar with the planar exposed surfaces of the standoffs. A semiconductor superstrate is secured to the first layer of electrically insulating material, the superstrate containing electrical devices. A connection connects the electrical devices contained in the superstrate to the electrical devices in the substrate.

Hybrids semiconductor circuit

A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.

Semiconductor hybrids and method of making same

About 6 to 20 micrometer resistivity N- (600 ohm-cm and above) silicon is epitaxially deposited on N+ (0.01 to 0.1 ohm-cm) substrates. The resistivity of the epitaxial layer is lowered to 5 to 60 ohm-cm using neutron activated doping. A 1 micrometer p-well process is utilized to build natural (unadjusted) PMOS transistors in the bulk silicon. These transistors operate in the subthreshold region where the threshold or turn on voltages have to match closely across a large device. N-channel transistors are fabricated in a P-well. The advantage of using neutron activated doped silicon is that the carrier concentration is very uniform and therefore threshold variations are much smaller than in transistors built in conventional doped silicon. The use of a neutron doped epitaxial layer on a P-well CMOS process provides a novel approach to control dopant uniformity and thus uniform transistor characteristics as well as providing a heavily doped conventional substrate to enhance resistance to CMOS latch-up.

P-well CMOS process using neutron activated doped N-/N+ silicon

Growing community of inventors

Sachse, TX, United States of America

Emily A Groves