Freescale Semiconductor,inc.

Emilio Quiroga

Mahibur Rahman

Conor O'Keeffe

Paul Kelleher

Charles LeRoy Sobchak

Samir J Soni

Diarmuid McSwiney

A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Electronic device, integrated circuit and method therefor

Methods, devices and systems are provided for word synchronizing multiple serial data bitstreams () with a serial framing signal (A). Offset values () are determined () from the relative locations of predetermined data correlation values () stored within the data buffers during a correlation mode to indicate the amount of skew observed between the framing channel and each of serial data channels. Data received during subsequent operation of each data stream is stored a buffer (), and the framing signal (A) is monitored to identify a boundary between data words. When a frame boundary occurs, parallel data is extracted from the buffer using the previously-stored offset values to compensate for bit skew between the data and framing channels.

Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface

A multirate processing circuit () with a resampling filter () to accept a sampled input signal () sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit () also has a discrete time processor () that receives the resampling filter output () and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor () further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output () at the integer power of two multiple of the second clock rate.

Fractionally related multirate signal processor and method

A digital clock generation circuit () and method of operation (). A digital clock () produces an output () with a first frequency or a second frequency. A clock control circuit () selectively sets the digital clock () to produce either the first frequency or the second frequency. An excess pulse counter () determines a number of pulses produced by the digital clock () at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit () removes, in response to the digital clock () changing from producing the second frequency to producing the first frequency, the number of pulses from the output () that were counted by the excess pulse counter ().

Digital clock generating circuit and method of operation

Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams () with a common clock signal (). Activity occurring in each bitstream is detected () for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected () for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted () from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.

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Lake Worth, FL, United States of America

Emilio Quiroga