D-wave Systems Inc.

1372934 B.c. Ltd

Emile M Hoskinson

Paul I Bunyk

Andrew Joseph Berkley

Trevor Michael Lanting

Richard G Harris

Kelly T R Boothby

Mark W Johnson

Mark H Volkmann

Christopher B Rich

Mohammad H S Amin

Mohammad H Amin

George E G Sterling

Loren J Swenson

Jed D Whittaker

Jan E S Johansson

Jeremy P Hilton

Andrew Douglas King

Evgeny A Andriyash

Anatoly Smirnov

Chunqing Deng

Alexandre Fréchette

Reuble Mathew

Min Jan Tsai

In a superconducting quantum processor, inductance is a characteristic of superconducting flux qubits and used to achieve coupling between qubits. In general, higher qubit energy scale results in better quantum processor performance. Energy scale of qubits can be increased by reducing inductance. For each Ising spin problem, qubit energy scale can be increased by determining the unused inductance-tuner range for each qubit and the minimum homogenized inductance achievable across all qubits, then adjusting the inductance-tuner to achieve the minimum homogenized inductance. When the inductance of a qubit is changed, there is a shift in the CCJJ bias at which quantum annealing is performed for that qubit. The variation in CCJJ bias shift can be compensated by computing the shift in CCJJ bias due to the applied inductance and applying a compensating CCJJ bias via the CCJJ offset DAC.

Systems and methods for increasing energy-scale by minimizing qubit inductance

Systems and methods for capacitance tuning of devices in quantum processors are described. One implementation is a quantum processor with a first current path having a first loop, a Josephson structure with at least one Josephson junction interrupting the first loop, a second current path connected to the first current path, and a flux bias. The second current path has a first node spaced from a second node, a capacitor separating the first node and the second node, and a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path. The flux bias is coupled to the voltage gain tuner and controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.

Systems and methods for tuning capacitance in quantum devices

Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.

Systems and methods for addressing devices in a superconducting circuit

Devices, systems, and methods that include a qubit coupled to a projective-source digital-to-analog converter (PSDAC) for projective measurement of the qubit. A change in flux state of the PSDAC from a first flux state to a second flux state generates a fast-flux step or fast-step waveform that can be applied to the qubit to perform projective measurement of the qubit. For a quantum processor that includes a set of qubits wherein each qubit is coupled to a respective PSDAC, a shared trigger line can activate each PSDAC to generate a respective fast-flux step or fast-step waveform. Synchronization devices can synchronize the fast-flux steps or fast-step waveforms, allowing for projective readout of the set of qubits.

Single flux quantum source for projective measurements

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a 'braided' pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

Systems and methods for superconducting devices used in superconducting circuits and scalable computing

Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

Systems and methods for degeneracy mitigation in a quantum processor

Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude &#x394;of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).

Systems and methods for coupling qubits in a quantum processor

Passive and actives approaches to mitigating the effects of spin-bath polarization are described and illustrated. Such may, for example, include at least partially depolarizing the spin-bath polarization, for instance by: performing an annealing cycle by the quantum processor to generate a final state of a qubit of the quantum processor; flipping the final state of the qubit of the quantum processor to an opposite state; and latching the qubit in the opposite state for a predetermined duration.

Superconducting quantum processor and method of operating same

In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an 'as designed' or 'as manufactured' physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.

Growing community of inventors

Vancouver, Canada

Emile M Hoskinson