Xilinx, Inc.

Emil S Ochotta

W Story Leavesley, Iii

William W Stiehl

Eric M Shiflet

Douglas P Wieland

William R Bell, Ii

A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.

Method and apparatus for circuit design closure using partitions

A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and, from a first application, invoking at least one plug-in software component configured to access the dependency management data for the circuit design. The method further can include identifying partitions of the circuit design that must be run during the incremental flow using the plug-in software component.

Plug-in component-based dependency management for partitions within an incremental implementation flow

A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.

Partition-based incremental implementation flow for use with a programmable logic device

Method and apparatus for controlling concurrent access to a data file. The data file is organized into a plurality of partitions, and a lock file that is accessible to the client applications is persistently stored. The lock file includes lock objects that correspond to the plurality of partitions, and each lock object indicates a lock status of the corresponding partition. The client applications perform an atomic file system operation on a persistent file system object when exclusive access is sought to the lock file. Successful completion of the atomic file system operation indicates that a client application has exclusive control over the lock file, and the lock file may thereafter be updated, the atomic operation undone, and access made to a selected partition.

Control of concurrent access to a partitioned data file

Method and apparatus for managing persistent data objects between persistent storage and memory. A plurality of the objects include one or more pointer values that reference other ones of the objects. Persistent storage pointer values in an object are swizzled to memory pointer values when the object is transferred from persistent storage to memory. The memory pointer values in an object to persistent storage pointer values are unswizzled when the object is transferred from memory to persistent storage. In generating a persistent storage address from a persistent storage pointer value, the persistent storage pointer value is multiplied by a selected multiplier.

Addressing objects in a large persistent storage address space

A modification to the available simulated annealing algorithm is provided to better utilize direct connects and other architecture-specific features of a Field Programmable Gate Array. A preferred embodiment comprises adding a template-based move to the SA move-set that recognizes a specific pattern or template in the user's design after mapping, and arranges the components into the optimal configuration for the specific template discovered. The present invention increases the intelligence of the SA move-set by selectively supplementing the random moves in the move-set with moves that produce locally good solutions.

Template-based simulated annealing move-set that improves FPGA architectural feature utilization

A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics. The direct connections of the invention are the preferred interconnect path between logic blocks because they substantially reduce the average interconnect delay, thereby allowing the programmable logic device to operate at a higher speed.

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Mountain View, CA, United States of America

Emil S Ochotta