Atmel Corporation

Other

Emil Lambrache

Benjamin Francis Froemming

George Smarandoiu

Duncan Curry

Richard F Pang

Gregg Stuart Nielson

Andrew K Au

Apparatus and methods for quickly switching active context between data pointer registers are disclosed. The apparatus can include a first register operable for storing a first data pointer and a second register operable for storing a second data pointer. A configuration register can provide a first signal specifying either the first or the second data pointer as an active data pointer. An instruction decoder can receive a data pointer instruction and output a second signal. The first and second signals can be independent from one another. Decoding logic coupled to the logic devices can output one of the first or second data pointers as the active data pointer in response to the first and second signals.

Switching data pointers based on context

A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array (); has a plurality of memory cells (), each of which is coupled to a unique array bitline (). A unique recovery transistor () coupled to each array bitline (). The recovery transistors () on odd bitlines () are coupled to a first and second voltage (), while the recovery transistors on even bitlines are coupled, to a first and third voltage (). During a write operation, each recovery transistor coupled to an unselected bitline is active during a write operation and a recovery operation, while each recovery transistor coupled; to selected bitline is active during a recovery operation. The first voltage () is sufficient to prevent parasitic coupling between the selected bitlines and the unselected bitlines during the write operation.

Use of recovery transistors during write operations to prevent disturbance of unselected cells

A sway capable bicycle has a bicycle frame firmly mounted on a sway-capable upper base mounted on a lower base and which has resilient members connecting each corner of the base support to the corresponding corner of the upper base.

Sway-capable stationary bicycle

A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions.

Microcontroller with low-cost digital signal processing extensions

A stack pointer is copied to a stack pointer base to debug stack underflow. A move instruction, used to initialize the stack pointer, is modified to additionally copy the stack pointer to a stack pointer base register. During a course of execution in a single context, the stack pointer base sticks to the initial base value while the stack pointer is altered by a succession of PUSH and POP instructions. By monitoring for equivalence in the stack pointer and the stack pointer base values, a balanced number of PUSH and POP instructions is detected. If an equal number of PUSH and POP instructions is detected and an additional POP instruction is programmed, a stack underflow condition exists, an exception condition signaled, and exception flag produced. The exception condition allows the stack to be protected from an excessive POP instruction retrieving data out of context and subsequent loss of stack data.

Stack underflow debug with sticky base

A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of tolerating an overvoltage, sustaining an electrical connection to an elevated voltage level, and producing an output voltage at an indigenous supply level. An initial pullup drive circuit is coupled to the plurality of output drive devices and produces an initial elevated drive voltage to the plurality of output drive devices. A sustain pullup circuit is coupled to the plurality of output drive devices and produces a sustained output voltage at the indigenous supply level.

High voltage tolerant port driver

Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

Fast read port for register file

A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential Vof an array VSS line by means of a comparator, allowing the array VSS line to electrically float until the potential Vis approximately equal to a reference potential V, and terminating the programming by de-coupling at least one of the current source and the potential source.

Array source line (AVSS) controlled high voltage regulation for programming flash or EE array

The same microcontroller chip is configured to be either a Target version or a Link version of a microcontroller. The Target version runs an application program. To debug the Target microcontroller, the Link version of the microcontroller functions as a master debug microcontroller to the slave Target microcontroller running the application program. The Link microcontroller runs an interface translator program between a Host computer that runs a debug program, and the Target microcontroller. The Link microcontroller communicates with the Target microcontroller using a fast, 2-wire interface. The Link microcontroller communicates with the Host computer through a general purpose interface.

Dual CPU on-chip-debug low-gate-count architecture with real-time-data tracing

A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.

Double byte select high voltage line for EEPROM memory block

A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array has a plurality of memory cells, each of which is coupled to a unique array bitline. A unique recovery transistor is coupled to each array bitline. The recovery transistors on odd bitlines are coupled to a first and second voltage, while the recovery transistors on even bitlines are coupled to a first and third voltage. During a write operation, each recovery transistor coupled to an unselected bitline is active during a write operation and a recovery operation, while each recovery transistor coupled to a selected bitline is active during a recovery operation. The first voltage is sufficient to prevent parasitic coupling between the selected bitlines and the unselected bitlines during the write operation.

Growing community of inventors

Campbell, CA, United States of America

Emil Lambrache