Synopsys, Inc.

Emil I Gizdarski

Rohit Kapur

Thomas W Williams

Frederic J Neuveux

Suryanarayana Duggirala

Nodari Sitchinava

Samitha Samaranayake

Peter Wohl

John A Waicukauski

Fadi Maamari

Andrea Costa

Wolfgang Meyer

Ruifeng Guo

Anubhav Sinha

Xiaolei Cai

The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.

Scan chain formation for improving chain resolution

A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.

Testable time-to-digital converter

Disclosed herein are method, system, and storage-medium embodiments for single-pass diagnosis of multiple chain defects in circuit-design testing. Embodiments include processor(s) to select a plurality of a scan chains in a circuit under test and determine presence of at least a first defect in the first scan chain, and a second defect in the first scan chain or in the second scan chain. The plurality of scan chains may include specific scan chains that each have respective pluralities of scan cells. Processor(s) may map the first defect to a first range of first scan cells, and the second defect to a second range of second scan cells. Based at least in part on a failing capture-pattern set, processor(s) may locate the first defect in a first scan cell of the first range, and the second defect in a second scan cell of the first range or the second range.

Single-pass diagnosis for multiple chain defects

Scan cells of a set of scan chains may be partitioned into at least two control groups of scan cells and at least two observe groups of scan cells. Adjacent scan cells in the set of scan chains may belong to different control groups. Each observe group may include at most one scan cell from each control group, and each control group may include at most one scan cell from each observe group. The control groups and observe groups may be used to perform defect localization on the set of scan chains.

Localization of multiple scan chain defects per scan chain

Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.

Cell-aware defect characterization by considering inter-cell timing

An integrated circuit (IC) design comprising a scan chain may be received, where stimulus values may be scanned-in and response values may be scanned-out through a scan path in the scan chain, where the scan path may include a first scan cell and a second scan cell such that the first scan cell is downstream with respect to the second scan cell. The scan chain may be modified to enable observation of a 0 and a 1 value in the first scan cell in presence of a defect in the second scan cell, or observation of a 0 and a 1 value in the second scan cell in presence of a defect in the first scan cell.

Integrated circuit design modification for localization of scan chain defects

A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where:

Reducing X-masking effect for linear time compactors

Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.

Power-aware dynamic encoding

Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester.

Augmented power-aware decompressor

Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Diagnosis and debug with truncated simulation

Diagnosis and debug using truncated simulation

Methods and apparatuses for generating compressed test data for use by a tester, decompressing the test data during test, and routing the decompressed test data into a set of scan chains within a circuit under test are described.

Linear decompressor with two-step dynamic encoding

Methods and apparatuses are described for decompressing and routing test data. Some embodiments feature an integrated circuit (IC) that includes two or more shift registers configured to shift in the test data. Each of the two or more shift registers can include two or more sequential elements configured such that a scan chain in the set of scan chains receives inputs from at most one sequential element in each of the two or more shift registers. At least one shift register in the two or more shift registers can be configured as a circular shift register. The IC can also include a logic network coupled between the two or more shift registers and the set of scan chains such that the set of scan chains receives the decompressed test data from the two or more shift registers via the logic network.

synthesizing circular decompressors

Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.

Method and apparatus for synthesis of multimode x-tolerant compressor

Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.

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Cupertino, CA, United States of America

Emil I Gizdarski