Lsi Logic Corporation

Emery O Sugasawara

Stefan Graef

V Swamy Irrinki

James McNames

Robert Madge

Kevin Cota

Sudhakar R Gouravaram

Daniel R Bockelman

W Robert Daasch

Donald J Esses

Mario Garza

Zafer S Kutlu

Kevin C Weaver

Dilip Vijay

Victer K Chan

Yogendra Ranade

Ronnie V Vasishta

Charles E Vonderach

Jeff Hall

Jay Hidy

Scott Franklin Keller

Dwight Manning

Mandar M Dange

Parthasarathy Rajagopalan

A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

Method and apparatus for avoiding dicing chip-outs in integrated circuit die

A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Statistical decision system

When designing an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal. Also, an electronic circuit description of a system is synthesized from a technology-independent description of the system. Specifically, a technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Utilizing a technology-independent system description incorporating a metal layer dependent attribute

A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.

Test limits based on position

A die including a corrosion monitoring feature is described. The die includes: (i) a surface including an active die region and a scribeline region that is adjacent the active die region; (ii) an insulating layer disposed above the surface and includes a first corrosion sensitive metal plug and a second corrosion sensitive metal plug in the scribeline region; and (iii) a metallization layer positioned above the insulating layer, the first corrosion sensitive metal plug and the second corrosion sensitive metal plug in the scribeline region and the metallization layer disposed above second corrosion sensitive metal plug is patterned to provide the metallization layer with a first opening extending from a top surface of the metallization layer down to a top surface of the second corrosion sensitive metal plug such that a solvent introduced above the top surface of the metallization layer flows into the second corrosion sensitive metal plug disposed below through the first opening in the metallization layer.

Corrosion sensitivity structures for vias and contact holes in integrated circuits

A method for improving the accuracy of quiescent current testing by reducing reliance on absolute quiescent current test limits. Initially, the device under test is placed into a static DC state in a traditional manner. Quiescent current is then measured with the power supply to the device set to a nominal operating voltage. Next, a fixed voltage lower than the nominal power supply voltage is applied to the integrated circuit in order to reduce the quiescent current consumed by the device. An additional quiescent current measurement is taken. The difference in quiescent current between the first and second measurements is then calculated. Additional quiescent current measurement(s) are also taken at increasing lower supply voltages. The differences in quiescent currents between each of these measurements is also calculated. After a sufficient number of measurements have been gathered, the resulting difference values are examined to determine the &ldquo;linearity&rdquo; of the quiescent current reduction. In an acceptable device, the lower power supply voltages cause the leakage or quiescent current inherent in the integrated circuit to decrease in a roughly exponential manner. Therefore, if the reduction in quiescent current is roughly exponential, it is generally assumed that the detected quiescent currents are a result of normal transistor effects. If the change in currents approximates a linear function, however, it is likely that the device under test contains a defect and the device is rejected.

Reduced voltage quiescent current test methodology for integrated circuits

An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts having a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact. The amount of the current being indicative of an amount of misalignment between layers of the integrated circuit die.

On-chip misalignment indication

A method for assigning signals to specific metal layers through the use of interconnect wire load models that are metal layer dependent. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process. A technology library for use in designing integrated circuits is provided. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values. The additional information influences the delay calculations of the synthesis process in such a way that the delay a signal encounters on a specific metal layer can be approximated very closely. Of significance to the present invention, a wire-metal layer attribute file is compiled by the synthesis process. The wire-metal layer attribute file output directs layout tools to route individual signals on specific metal layers. Alternatively, the layout tool can utilize the wire-metal layer attribute file to determine a set of acceptable routing layers, allowing an optimal route for a signal to be chosen in relation to the requirements of other signals.

Method of selecting and synthesizing metal interconnect wires in integrated circuits

Process monitoring circuitry according to the invention incorporates test structures placed across an integrated circuit die to monitor the performance of the fabrication process across the die. The integrity of the semiconductor fabrication process used to manufacture a particular integrated circuit is ascertained by comparing data extracted the test structures by automated test equipment (ATE) to simulation values. In one embodiment in the invention, the process monitoring circuitry comprises inverters arranged in a generally linear fashion. The inverters may be composed of simple CMOS inverters or other logic gates configured as inverters. The logic gates are arranged in horizontal and/or vertical test paths in which the gates are disposed across various sections of the integrated circuit die. An input test pad and an output test pad for each test path are provided at opposing sides of the integrated circuit die. In one alternate embodiment of the invention, multiplexing circuitry is utilized at the input and output test pads in order to minimize the impact of the process monitoring circuitry. The various test paths may incorporate comparatively lengthy metal routing lines, allowing accurate measurement of metal interconnect delays.

Performance monitoring circuitry for integrated circuits

Process monitoring circuitry according to the invention incorporates additional routing structures that approximate signal delays due to long metal routing paths. The additional process monitor circuitry builds upon existing approaches without increasing the die size of an integrated circuit through the utilization of excess silicon space available between the bonding pads and the scribe lines of an integrated circuit wafer. More specifically, supplemental metal routing lines and vias are included in the delay paths of process monitor circuitry and located on the integrated circuit such that impact to other metal signal lines/vias used in the actual design is minimized. The supplemental metal routing lines are disposed in unused routable silicon space, such that no silicon area penalty is suffered as a result of having long metal routing lines. During the testing of an integrated circuit incorporating the improved process monitor circuitry, test signals for determining the relative strength of different types of transistors of the integrated circuit are extracted. These test signals are compared to simulated delay values that reflect the delays of the additional metal routing lines and vias. Extreme process variations cause the values provided by the process monitor's circuitry to fall outside the set of permissible values determined through three-dimensional simulation. Thus, process monitoring circuitry according to the present invention improves the fault coverage provided by the testing procedures for an integrated circuit by providing information regarding process variations in different metal layers, and may be utilized as a surrogate for observable path testing.

Process monitor circuitry for integrated circuits

Corrosion sensitivity structures for vias and contact holes in

A method for improving the accuracy of quiescent current estimation for integrated circuits. When used with a CMOS process, the method involves selecting transistors having a polysilicon gate length corresponding to the minimum length permitted by process design rules. For each of the selected transistors, the intersection of the width of the polysilicon gate and the active area of the transistor is calculated. The widths of all of the selected minimum length devices are summed to generate a total width dimension value. The total width dimension value is multiplied by a predetermined quiescent current per unit width conversion value to produce an estimate of the quiescent current drawn by the integrated circuit. In an alternate embodiment of the invention, the total width dimension value is multiplied by a range of predetermined quiescent/leakage current per unit width values representing a range of testing conditions and temperatures. The method of the invention can be implemented as a stand-alone software routine or integrated within a design verification or test pattern generation tool. The accuracy of quiescent current estimation provided by the invention permits realistic test values to be established, thereby enhancing both quality and yield of semiconductor processes.

Method for estimating quiescent current in integrated circuits

A computer-based test method and apparatus for measuring DC current drawn by an integrated circuit. The apparatus has a plurality of current measurement ranges and is first initialized to a selected one of the measurement ranges. Next, the apparatus measures the DC current drawn by the integrated circuit in the selected measurement range and increments the selected measurement range if the measured DC current is out of the selected measurement range. The apparatus repeats the steps of measuring and incrementing until the measured DC current is in the selected measurement range. The measured DC current is then compared to a specification limit for the integrated circuit.

Automatic ranging apparatus and method for precise integrated circuit

A method for automated placement of markers or probe points adjacent to critical timing paths in an integrated circuit design. The markers aid in identifying critical path interconnect lines for purposes of failure analysis or design verification. In a method according to the invention, timing information related to various signal paths in an integrated path is analyzed to isolated critical timing paths. Once a signal path is determined to be a critical timing path, layout data for the critical path is extracted from a layout database. An unused area(s) is then located adjacent to the critical path. Marker information is next inserted into the unused area(s) of the layout database. The act of inserting marker information is performed by a specialized software tool capable of modifying a layout database. Alternatively, existing automated floorplanning or layout tools, or other electronic design automation (EDA) tools, whether proprietary or industry standard, are modified to insert the marker information. The marker information causes markers to be fabricated at strategic points along the critical path in the unused areas without violating design rules. Hence, upon visual inspection of the integrated circuit, a failure analyst can readily locate the markers and identify critical paths.

Probe points and markers for critical paths and integrated circuits

A method for removing solder from the leads of ICs including immersing the IC in an acid solution. The acid solution dissolves the excess solder on the IC leads. The acid solution is preferably a hydrogen chloride solution containing about 38% hydrogen chloride and 62% water. The acid solution, however, can contain up to 50% hydrogen chloride. After the IC is immersed for a period of time, preferably ten minutes, it is removed from the acid solution and rinsed with water. The IC is rinsed so as to remove any remaining acid solution residue. Rinsing for 5 minutes or more typically ensures removing all of the acid solution. The IC is then inspected to determine whether substantially all of the excess solder is removed from the IC leads. If excess solder still remains on the IC leads, the IC is reintroduced into the solder removing process including immersing the IC in the acid solution, rinsing the IC with water, and inspecting the IC. The process is repeated until substantially all, if not all, of the excess solder is removed.

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Pleasanton, CA, United States of America

Emery O Sugasawara