Gte Laboratories Incorporated

Textron Systems Corporation

Emel S Bulat

Marvin J Tabasky

Howard C Choe

Charles Herrick

Scott J Butler

Brian M Ditchek

Richard M Klein

Maureen A Sullivan

Brian T Devlin

An acoustic system has an acoustic sensor and a processing circuit. The acoustic sensor includes a base, a microphone having a microphone diaphragm supported by the base, and a hot-wire anemometer having a set of hot-wire extending members supported by the base. The set of hot-wire extending members defines a plane which is substantially parallel to the microphone diaphragm. The processing circuit receives a sound and wind pressure signal from the microphone and a wind velocity signal from the hot-wire anemometer, and provides an output signal based on the sound and wind pressure signal from the microphone and the wind velocity signal from the hot-wire anemometer (e.g., accurate sound with wind noise removed). The configuration of the hot-wire extending members defining a plane which is substantially parallel to the microphone diaphragm can be easily implemented in a MEMS device making the configuration suitable for miniaturized applications.

Systems and methods for sensing an acoustic signal using microelectromechanical systems technology

A junction field effect transistor, specifically a static induction transistor. The N-type source regions are formed as two zones. First, relatively lightly doped first zones are formed by ion-implanting doping material relatively deeply into the semiconductor material. Then relatively heavily doped second zones are formed by ion-implanting doping material to a relatively shallow depth within the first zones to leave portions of the first zones interposed between the second zones and the remainder of the semiconductor material. The resulting devices exhibit reduced gate-drain junction capacitance at low drain bias voltages thereby improving device capacitance linearity.

Field effect transistor and method of fabricating

Method of fabricating a junction field effect transistor employing self-alignment techniques. The active regions of the device are defined by a relatively thin thermally-grown isolating silicon oxide layer at the surface of a silicon body. After the active source and gate regions of the device as defined by the thermally-grown isolatign silicon oxide are formed in the silicon, a layer of deposited silicon oxide is formed over the thermally-grown silicon oxide. This method provides a thick dielectric layer as well as control of the horizontal dimensions of the source and gate contacts.

Method of fabricating field effect transistors

A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.

Junction field effect transistor with SiGe contact regions

In the fabrication of a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity N-type silicon. A plurality of elongated parallel grooves separated by interposed ridges are formed by reactive ion etching. A layer of silicon oxide is grown on all exposed surfaces including the side walls and bottoms of the grooves. Fluorine is ion implanted into the silicon oxide. The grooves are filled with deposited silicon oxide or polycrystalline silicon, and material is removed to form a flat planar surface with the silicon at the surfaces of the ridges exposed. P-type doping material is ion implanted into alternate (gate) ridges. The wafer is heated to diffuse the P-type doping material and form gate regions. Heating also activates the implanted fluorine ions which react with unbonded silicon atoms at the silicon oxide-silicon interface thus quenching vacant bond sites. N-type doping material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, source ridges, and the bottom of the substrate.

Method of manufacturing semiconductor devices

In fabricating a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is marked in a pattern to expose a plurality of elongated surface areas. The wafer is subjected to reactive ion etchings in SiCl.sub.4 and Cl.sub.2 and subsequently in Cl.sub.2 to form parallel grooves with rounded intersection between the wide walls and bottoms of the grooves. Ridges of silicon are interposed between grooves. A layer of silicon oxide is grown on all the silicon surfaces. The grooves are filled with deposited silicon oxide and silicon oxide is removed to form a planar surface with the upper surfaces of the ridges. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves, N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, source ridges, and the bottom of the substrate.

Method of manufacturing static induction transistors

Method of fabricating junction field effect transistor

A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. Parallel grooves are etched through the low resistivity N-type layer into the high resistivity N-type layer forming interposed ridges of silicon. When fabricating junction gate devices, P-type zones are formed at the end walls of the grooves by ion implantation. A layer of silicon oxide is formed on the side walls of the grooves exposing the silicon at the end walls of the grooves and at the surfaces of the ridges. A layer of a silicide-forming metal, specifically cobalt, is deposited. A rapid thermal annealing treatment is performed which causes the cobalt to react with the silicon and form cobalt silicide at the cobalt-silicon interfaces. The cobalt does not react with the silicon oxide at the side walls of the grooves. The unreacted cobalt is removed by an etching solution which does not attack the cobalt silicide. Metal layers are placed on the cobalt silicide to increase its conductivity as contact members.

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Framingham, MA, United States of America

Emel S Bulat