Micron Technology Incorporated

Stmicroelectronics S.r.l.

Other

Emanuele Confalonieri

Danilo Caraccio

Daniele Balluchi

Paolo Amato

Marco Dallabora

Marco Sforzin

Federico Tiziani

Nicola Del Gatto

Luca Porzio

Giulio Albini

Roberto Izzi

Gianfranco Ferrante

Carla Giuseppina Poidomani

Antonino Caprì

Graziano Mirichigni

Stephen S Pawlowski

Carlo Lisi

Patrick Alan Estep

Marco Ferrario

Massimiliano Mollichelli

Corrado Villa

Lorenzo Bedarida

Dionisio Minopoli

Stefan Frederik Schippers

Federica Cresci

Francesco Mastroianni

Angelo Alberto Rovelli

Massimiliano Patriarca

Manuela Scognamiglio

Stefano Ratti

Simone Corbetta

Antonino Caprí

Davide Cascone

Sara Villa

Gianfranco Santopietro

Angelo Clemente Scardilla

Stefano Claudio Roseghini

Gary G Lazarowics

Daniele Vimercati

Massimo Iaculo

Simone Bartoli

Giuseppe D'Eliseo

Mauro Luigi Sali

Francesco Falanga

Ornella Vitale

Chris Bueb

Antonino Geraci

Vincenzo Dima

Antonio Geraci

Yu-Sheng Hsu

Massimiliano Scotti

Michela Spagnolo

Nicola Rosito

Yaw Fann

Giuseppe Russo

Massimiliano Turconi

Antonino Capri

Roberto Versari

Luigi Bettini

Paolo Turbanti

Systems, apparatuses, and methods related to a memory controller for unloaded cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache. The cache can include a cache sequence controller configured to determine a quantity of a pending cache look-up operations, determine the quantity satisfies an unloaded bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Unloaded cache bypass

An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups, and the memory controller comprises respective independent caches corresponding to the plurality of channel groups.

Controller cache architeture

A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Rows of the memory device can also be updated based on a duration of time between receipt of the activation command for the row and a pre-charge command for the row. Row of the memory device clan further be updated utilizing a pair of counters that implement a ping pong mechanism to retain data between different consecutive durations of time.

Row tracking for row hammer mitigation

Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.

Adjustable timer component for semiconductor devices

An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

Memory controller architecture

Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

Managed memory systems with multiple priority queues

Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Cache bypass

A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

Apparatus for redundant array of independent disks

An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

Controller architecture for reliability, availability, serviceability access

Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

Controller to alter systems based on metrics and telemetry

Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.

Controller for managing multiple types of memory

A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

Memory controller for managing raid information

A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

Controllers and methods for accessing memory devices via multiple modes

Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.

Read data path

Systems, apparatuses, and methods related to access request management using sub-commands. Access requests received from a host system can be managed using a respective set of sub-commands corresponding to each access request and whose status can be tracked. Tracking how far access requests are processed at a fine granularity (of sub-commands) can provide efficient management of the access requests that can reduce a gap latency in processing multiple access requests.

Access request management using sub-commands

Growing community of inventors

Lesmo, Italy

Emanuele Confalonieri