Infineon Technologies Ag

Infineon Technologies Austria Ag

Emanuele Bodano

Joachim Pichler

Luca Bizjak

Maria Lagioia

Cristian Garbossa

Marco Flaibani

Stefano Marsili

Marco Piselli

Andrea Vecchiato

Andrea Morra

Dirk Hammerschmidt

Peter Bogner

Angela Kessler

Michael Lenz

Andrea Logiudice

Stefan Hermann Groiss

Robert Fehler

Giorgio Chiozzi

Simone Massaro

Vratislav Michal

Volha Kharko Subotskaya

Martin Benisek

Maurizio Inversi

Salvatore Piccolella

Mark Schauer

Nicola Macri

Massimiliano Fieni

Andrea Congiu

Christian Garbossa

Kushal Kshirsagar

A semiconductor package includes a laminate package substrate, first and second power transistor dies embedded within the laminate package substrate, a driver die embedded within the laminate package substrate, a plurality of I/O routings electrically connected with I/O terminals of the driver die, a switching signal pad electrically connected with a second load terminal of the first power transistor die and a first load terminal of the second power transistor die, and a shielding pad that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies.

Embedded package with shielding pad

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Over current protection concept for negative load current of power device gate drivers

A power stage having a power transistor coupled between a power supply and a switching node; a charge pump coupled between the power supply and a gate of the power transistor; and a gate driver configured to charge the gate of the power transistor until the gate voltage reaches a predefined voltage, and further charge the gate of the power transistor from the charge pump.

Power stage with sequential power transistor gate charging

According to an embodiment, a method of operating a switching power supply includes applying a periodic switching signal to a first switch that is coupled to an output node, detecting an offset delay between applying the periodic switching signal and a change in voltage of the output node, calculating a corrected midpoint of a half phase of the periodic switching signal based on the offset delay, generating a sampling pulse based on the corrected midpoint, and sampling a current at the output node according to the sampling pulse.

System and method for switched power supply with delay measurement

A method of operating a switched-mode power supply (SMPS) includes starting up the switched-mode power supply by determining a rate of increase of a duty cycle of a pulse width modulated (PWM) signal based on an input voltage and a switching frequency of the SMPS; and generating the PWM signal having the duty cycle in accordance with the determined rate of increase.

System and method for starting a switched-mode power supply

In accordance with an embodiment, a circuit includes: a gate drive circuit; an output transistor, and a gate coupled to the gate drive circuit; a normally-on transistor including a load path coupled to the gate drive circuit and to the gate of the output transistor; and a pull-up device, where the output transistor is configured to provide a test leakage current in a test mode when a measurement voltage is applied to a current test node coupled to the gate of the output transistor and a turn-off voltage is applied to the gate of the normally-on transistor; and the gate drive circuit is configured to provide a gate drive voltage to the gate of the output transistor in a nominal operation mode when a voltage of the gate of the normally-on transistor is pulled-up to a voltage of the pull-up node via the pull-up device.

Test circuit for stress leakage measurements

System and method for switched power supply current sampling

Methods and devices are provided wherein a change of a mode of operation is performed based on a time where both switches of a first and a second switch are open.

Voltage converter for first and second modes of operation

In accordance with an embodiment, a method for controlling a switched-mode power supply (SMPS), includes receiving a measurement of a supply voltage input of the SMPS, determining a change in the supply voltage input over time based on receiving the measurement, comparing the determined change in the supply voltage input with a predetermined threshold value and applying a correction factor to an integrator within a feedback control loop of the SMPS based on the comparing.

System and method for controlling a duty cycle of a switched-mode power supply

A converter circuit is described comprising a switch circuit configured to provide an output voltage, a control circuit comprising an analog control portion and a digital control portion and a noise generator configured to generate white noise, wherein the noise generator is configured to supply the generated white noise to the digital control portion of the control circuit and wherein the control circuit is configured to control the switch circuit based on the white noise.

Converter circuit and method for converting an input voltage to an output voltage using a white noise generator

A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.

Analog-to-digital converter and control circuit with a low quiescent current at low load

Devices and methods are provided in which a driver is supplied via a first current path and a second current path which can comprise a switching element.

Driver circuit

Preferred embodiments of the present invention are a switching converter, an integrated circuit package, and method for controlling a switching converter. An embodiment of the invention is a switching converter comprising a first compensation network having a first node coupled to an error voltage and a second node coupled to electrical ground and a second compensation network having an input coupled to the error voltage. A frequency domain transfer function of the first compensation network comprises a first zero and a plurality of first poles, and a frequency domain transfer function of the second compensation network comprises a second zero and a second pole.

Switching converter and method to control a switching converter

A system and method for adapting a width of a clocking pulse for clocking a DC-DC converter, wherein the width of the clocking pulse is selected based upon the duty cycle of the DC-DC converter. When the DC-DC converter operates below a predefined threshold duty cycle, a clocking pulse of a first width is selected to allow operation of the converter at a minimum predefined duty cycle with a clocking frequency that minimizes output voltage ripple. The first width corresponds to an on-time of a switching transistor of the DC-DC converter when the converter is operated at the minimum duty cycle. When the DC-DC converter operates above the predefined threshold duty cycle, a clocking pulse of a second width is selected to allow operation of the converter at high duty cycles while simultaneously avoiding missed inductor current pulses and generation of sub-harmonic voltage oscillations.

System and method for adapting clocking pulse widths for DC-to-DC converters

A system for supplying current to a load is disclosed. One embodiment provides a switching converter for providing a load current to the load. The switching regulator includes a switching circuit. A current control unit generates a modulated current control signal representing a desired load current. The switching circuit is driven dependent on the modulated current control signal. A logic circuit receives a pulse-width-modulated control signal representing a desired dimming ratio and is configured to generate a gate signal for driving the switching circuit dependent on the current control signal during a duty cycle of the pulse-width-modulated control signal. The logic circuit is configured to activate the switching converter, independent on the state of the current control signal, at the beginning of the duty cycle of the pulse-width-modulated control signal.

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Villach, Austria

Emanuele Bodano