Cypress Semiconductor Corporation

Emad Hamadeh

Pidugu L Narayana

Stefan-Cristian Rezeanu

James D Allan

Eric Wolf Gross

Sangeeta Thakur

Vijay Srinivasaraghavan

Robert W Manning

An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.

Distributed test architecture for multiport RAMs or other circuitry

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports

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Santa Clara, CA, United States of America

Emad Hamadeh