Rambus Inc.

Bryte, Inc.

Wimm Labs, Inc.

Other

Google Inc.

Highlands Corporation

Ely K Tsern

Frederick Abbott Ware

Craig Edward Hampel

Richard E Perego

Richard Maurice Barth

Donald C Stark

Stefanos Sidiropoulos

Paul G Davis

Ian P Shaeffer

Mark A Horowitz

Scott C Best

Thomas Vogelsang

Kevin S Donnelly

John Eric Linstadt

Steven Cameron Woo

Billy Wayne Garrett, Jr

Brian S Leibowitz

Bruno Werner Garlepp

Thomas J Giovannini

Fredrick A Ware

Kenneth Lee Wright

Bradley A May

Todd W Bystrom

Suresh Rajan

Jonathan Farringdon

John Tompane

Wayne Frederick Ellis

Pak Shing Chau

Clemenz L Portmann

Ramprasad Satagopan

Fred Ware

Jared L Zerbe

Andrew V Anderson

James A Gasbarro

Akash Bansal

Thomas J Holman

Kishore Ven Kasamsetty

J James Tringali

John Welsford Brooks

Thomas J Sheffler

Catherine Yuhjung Chen

Abhijit Mukund Abhyankar

Belgacem Haba

David Nguyen

Donald Victor Perino

Abhijit Mukun Abhyankar

David Mooring

Srinivas Nimmagadda

Richard Tompane

Jeffrey D Mitchell

William Burnett

Carl William Werner

John Bradly Dillon

Nancy David Dillon, Legal Representative

Timothy Chang

Dave Mooring

Wai-Yeung Yip

Mark Handel

John Yan

Jeff Mitchell

Adam Hamel

Don Stark

Megan Tsern

Michael Mooring

Peter D MacWilliams

Gary Bela Bronner

David A Secker

Wendemagegnehu Beyene

Nitin Juneja

Alissa M Fitzgerald

Nancy David Dillon

By Nancy David Dillon

Thomas A Giovannini

Crag E Hampel

Wai-Yeng Yip

Matthew Walker

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Memory system topologies including a memory die stack

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

High-performance, high-capacity memory systems and modules

Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

Memory system with threaded transaction support

A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

DRAM retention test method for dynamic error correction

A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Memory repair method and apparatus based on error code tracking

A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

Memory component with adjustable core-to-interface data rate ratio

The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

High performance persistent memory

A bed may provide pneumatic effects. An array of pumps may be used in providing the pneumatic effects. In some embodiments less than all of the pumps may be operated to provide some of the pneumatic effects, and in some such embodiments no individual pump may be able to provide others of the pneumatic effects, and in some or other such embodiments all of the pumps may be required to provide at least one of the pneumatic effects.

Sleep platform pneumatics management system

A bed integrates sensors and other inputs to detect specific sleep environment conditions including point-specific pressure and/or temperature conditions. The bed includes a controller for commanding actuator or other devices to adjust these conditions. The controller may do so based on reference patterns for conditions and profiles of desired conditions. Information regarding the conditions may be provided to a remote computer, which may analyze the conditions and provide revised profiles of desired conditions.

Adaptive sleep system using data analytics and learning techniques to improve individual sleep conditions

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Memory controller with error detection and retry modes of operation

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Data transmission using delayed timing signals

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

Memories and memory components with interconnected and redundant data interfaces

A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Memory controller supporting nonvolatile physical memory

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Growing community of inventors

Los Altos, CA, United States of America

Ely K Tsern