Inmos Limited

Sgs-thomson Microelectronics Limited

Elwyn P Wakefield

Christopher Paul Walker

A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.

Semiconductor chip packaging having printed circuitry or printed circuit

The present invention proposes a method of manufacturing a ball grid array printed circuit board (210) that comprises the following steps: fabricating a printed circuit board, PCB, that comprises a matrix of ball grid array PCBs, each ball grid array PCB of the matrix is separated from its neighbors by the width of an electroplating tie bar (230); stamping the matrix of ball grid array PCBs for separating them and for forming an aperture (320) that is substantially centralized within each of them; preparing a metal sheet (510), onto which a semiconductor device (130) is mechanically attached; mechanically attaching a singularized ball grid array PCB to the metal sheet; and molding about the semiconductor device and a portion of the ball grid array PCB a protective material (140) that is substantially planar with respect to the ball grid array PCB.

Method of manufacturing a ball grid array package

An electrical assembly comprises an electrical component having an array of contact bumps. The component is mounted on a multilayer printed circuit board having a plurality of conducting pins located in holes in the board and having pointed ends projecting above the board and making electrical contact with the bumps on the component.

Circuit connection in an electrical assembly

A semiconductor chip package comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip packages.

Semiconductor chip packages

A semiconductor chip package comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip package.

A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externaly of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.

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Bristol, United Kingdom

Elwyn P Wakefield