Inphi Corporation

Clariphy Communications, Inc.

Elvio Adrian Serrano

Oscar Ernesto Agazzi

Mario Rafael Hueda

Diego Ernesto Crivelli

Hugo Santiago Carrer

Martin Ignacio Del Barco

Alfredo Javier Taddei

Norman L Swenson

Damian Alfonso Morero

Vadim Gutnik

Paul Voois

Ramiro Rogelio Lopez

Jorge Manuel Finochietto

Matias German Schnidrig

Mauro Marcelo Bruni

Federico Nicolas Paredes

Martin Carlos Asinari

Facundo Abel Alcides Ramos

Martin Serra

Pablo Gustavo Quiroga

Roman Antonio Arenas

Alejandro Javier Schwoykoski

Pablo Gianni

Ariel Pola

Ramiro Matteoda

Mario Alejandro Castrillon

Adrián Ulises Morales

María Laura Ferster

Maria Laura Ferster

Ulises Morales

Laura Maria Ferster

Alejandro Castrillon

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Coherent transceiver architecture

A receiver for fiber optic communications.

High-speed optical communications system

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Growing community of inventors

Cordoba, Argentina

Elvio Adrian Serrano