Samsung Electronics Co., Ltd.

Samsung Israel Research Corporation

Elona Erez

Jun Jin Kong

Avner Dor

Moshe Twitto

Yaron Shany

Shay Landis

Jun-Jin Kong

Michael Erlihson

Jong-Won Lee

Evgeny Blaichman

Eran Hof

Shmuel Dashevsky

Yoav Shereshevski

Noam Livne

Michael Kara-Ivanov

Iddo Naiss

Guy Inbar

Keon Soo Ha

Dashevsky Shmuel

Moshe Ben Ari

A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Nonvolatile memory devices and methods of controlling the same

A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

Storage devices including logical to physical address mapping and methods of operating

A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}of a j-th layer code and predefined syndrome {tilde over (s)} of length n&#x2212;{tilde over (k)}, where the first n-kcoordinates are zero, n is a length of a codeword c of a first layer BCH code Cof dimension {tilde over (k)}, codeword c satisfies {tilde over (H)}c={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n&#x2212;{tilde over (k)})(n&#x2212;{tilde over (k)}) such that R{tilde over (H)}=(A|I), where A is an arbitrary matrix, R=(Q|T), where Q has n&#x2212;kcolumns Tand has k&#x2212;{tilde over (k)}columns; finding a vector c&#x2212;(a b) where a is a vector of length {tilde over (k)}and b is a vector of length n&#x2212;{tilde over (k)}; and solving where a=0 and b=Ts, and codeword c is nonzero only on the last n&#x2212;{tilde over (k)}=n&#x2212;kbits.

Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID)

A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vectorof a new stage 0 binary BCH codewordover a field GF(2) that comprises &#x394;t syndromes of length m bits, wherein the syndrome vectorcomprises l-th Reed-Solomon (RS) symbols of &#x394;t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n&#x2212;1; and multiplyingby a right submatrix &#x168; of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by t, wherein the new binary BCH codeword is=&#x168;&#xb7;.

Efficient generalized tensor product codes encoding schemes

A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

Mapping bits to memory cells using sector spreading

A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.

Method of operating memory device using pseudo-random functions, memory device using the same and memory system including the device

A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device. The difference between the write data sector and its respective paired data sector is stored in an unoccupied portion of the corresponding physical page of the flash memory device.

Flash memory device including deduplication, and related methods

A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

Method and apparatus for encoding and decoding data in memory system

A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.

Method of similarity testing by syndromes and apparatus therefore

Systems and methods of determining a similarity between data units in a nonvolatile memory are disclosed. One method includes obtaining first and second data units and dividing the first and second data units into a first plurality of non-overlapping chunks of data and a second plurality of non-overlapping chunks of data. The method further includes determining a first plurality of values and a second plurality of values associated with the chunks, and determining a similarity between the first second data units based on the first plurality values and of the second plurality of values. In one example embodiment, a similarity between an incoming data unit and another data unit is determined based on the number of buckets storing an incoming index value and another index value associated with the another data unit. A plurality of buckets in a table is determined based on a selected plurality of hash values.

Nonvolatile memory systems configured to use deduplication and methods of controlling the same

At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

A method for protecting encoded data from algebraic manipulation includes receiving a data word s&#x3b5;Kto be protected, randomly selecting two integers a &#x3b5;{0, . . . , q&#x2212;1} and b &#x3b5;{0, . . . , &#x221a;q&#x2212;1}, finding a point (&#x3b1;, &#x3b2;) on a Hermitian curve over a field Fthat corresponds to the randomly selected integers (a, b) from a mapping (a, b)(&#x3b1;, &#x3b2;)=(u, uz+v), where and z is an element of the field Fof unit trace, and where &#x3b3;is a fixed primitive element of the field Fand &#x3b3;is a primitive element of a field FF, and calculating a sum f(&#x3b1;, &#x3b2;)=&#x3b1;&#x3b2;+&#x3a3;&#x3b1;&#x3b2;kfor a set of d+1 integers pairs I ={(i,j)}, where the encoded word is a triple (s, (&#x3b1;, &#x3b2;),f(&#x3b1;, &#x3b2;)).

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Ramat Gan, Israel

Elona Erez