Huawei Technologies Co., Limited

Elnaz Ebrahimi

Ehsan Khish Ardestani Zadeh

Wei-Yu Chen

Liang Peng

An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.

Growing community of inventors

San Jose, CA, United States of America

Elnaz Ebrahimi