Intel Corporation

Other

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Mark Jay Charney

Jesus Corbal

Bret L Toll

Abhishek R Appu

Joydeep Ray

Altug Koker

Zeev Sperber

Alexander F Heinecke

Prasoonkumar Surti

Subramaniam M Maiyuran

Amit Gradstein

Christopher J Hughes

Raanan Sade

Milind Baburao Girkar

Varghese George

Ben J Ashbaugh

Dan Baum

Vasanth Ranganathan

Simon Rubanovich

Venkateswara Rao Madduri

Balaji Vembu

Nicolas C Galoppo Von Borries

Aravindh V Anantaraman

Kamal Sinha

Ankur N Shah

Xiaoming Chen

Chandrasekaran Sakthivel

Mike MacPherson

Anbang Yao

Sara S Baghsorkhi

Linda L Hurd

Menachem Adelman

Lakshminarayanan Striramassarma

Devan Burke

Deepak Shashidhar Vembar

Dukhwan Kim

Murali Ramadoss

Ping Tak Tang

Travis T Schluessler

Jacek Kwiatkowski

John Charles Weast

Eriko Nurvitadhi

Peter L Doyle

Kshitij Arun Doshi

Justin E Gottschlich

Scott R Janus

Nikos Kaburlasos

Sanjeev S Jahagirdar

Adam T Lake

Atsuo Kuwahara

Rajkishore Barik

John H Feit

Hugues Labbe

Thomas Willhalm

Kai Xiao

Mikhail Plotnikov

Tatiana Shpeisman

Edward Thomas Grochowski

James M Holland

Vinodh Gopal

Jeffery S Boles

Tsung-Han Lin

Michael Apodaca

Nadathur Rajagopalan Satish

Feng Chen

Gabor Liktor

Narayan Srinivasa

Martin Guy Dixon

Karthik Vaidyanathan

Kiran Chand Veernapu

Robert Dale Cavin

Eric W Mahurin

Rajesh Poornachandran

Wajdi K Feghali

James D Guilford

Jason W Brandt

David M Puffer

Ingo Wald

Tomer Bar-On

Wenyin Fu

Stephen H Gunther

Selvakumar Panneer

Daniel Pohl

David B Papworth

Abhishek Venkatesh

Amit Bleiweiss

Rajesh M Sankaran

Guei-Yuan Lueh

Carsten Benthin

James A Valerio

Wei W Wang

Cheng C Wang

Youfeng Wu

Ravishankar Iyer

Eric C Samson

Boris Ginzburg

Narayan Biswal

Stanley J Baran

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Compute optimizations for neural networks

An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Machine learning accelerator mechanism

Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.

Multicore processor with each core having independent floating point datapath and integer datapath

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Prefetch status notification for memory prefetching

Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Implicit fence for write messages

Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.

Systems, methods, and apparatuses for dot production operations

An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

Efficient data sharing for graphics data processing operations

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Sparse optimizations for a matrix accelerator architecture

Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

Systems and methods to store a tile register pair to memory

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

Graphics system with additional context

Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the first and second matrices, broadcast up to two NZ elements at a time from each row of the first matrix and each column of the second matrix to a processing engine (PE) grid, each PE to multiply and accumulate matching NZ elements of the first and second matrices with corresponding elements of the third matrix. Each PE further to store an NZ element for use in a subsequent multiplications.

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

Systems, methods, and apparatus for tile configuration

Growing community of inventors

Chandler, AZ, United States of America

Elmoustapha Ould-Ahmed-Vall