Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Elmer W Carroll

George J Barlow

James W Keeley

Arthur Peters

Richard C Zelley

Virendra S Negi

David E Cushing

Chester M Nibby, Jr

Victor M Morganti

James F Bertone

Wallace A Martland

Edward Hutchings

A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.

Data processing system having a bus command generated by one subsystem

A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources which provide apparatus for indicating the status of power and temperature, booting the subsystems, testing the subsystems, timing central subsystem functions, and allowing local and remote maintenance access to the subsystems. The system management facility receives commands from the central subystem to read from and write into the timers as well as to read the status of the overall system. The system management facility generates special commands to the central subsystem to indicate when the timers have decremented to ZERO as well as special commands to aid in hardware and software debugging.

Multiprocessor system with centralized initialization, testing and

In a data processing system, a data processing unit contains data processing logic including shadowed functional registers for storing the data being processed. The units also include fault monitoring logic, including, for each shadowed functional register, a shadowing copy register connected in parallel from the corresponding shadowed register to receive and store a copy of the data resident in the shadowed register. Test logic is connected from the shadowed and shadowing registers for comparing the data resident in the shadowed and shadowing registers and providing indications of possible faults in the data processing logic. The shadowed and shadowing registers are connected in a serial scan chain through a serial scan data path. The integrity of the fault monitoring logic is tested by serially shifting, or scanning, known test patterns of bits through the serial scan chain comprised of the shadowed registers and shadowing registers. A first set of patterns are selected so that the test patterns themselves should not induce any errors to appear to the comparison logic so long as the the test logic is correct, so that any errors that are detected are due to a fault in the test logic. A second set of test patterns are selected to induce errors to appear as the patterns are shifted, bit by bit, through the scan chain. The first patterns thereby determine that there are not errors in the fault monitoring logic itself, and the second patterns that the fault monitoring logic is detecting errors correctly.

Method and apparatus for integrity testing of fault monitoring logic

A method for performing initial testing of a system wherein, in response to power on of the system, the control store of a central subsystem is loaded with a testing microinstruction program for internal testing of the central subsystem and the testing program executed. Upon completion of the testing program, the central subsystem operating programs are loaded into the control store, and control of the data processing system is transferred to the system programs.

Method for performing quality logic tests on data processing systems by

A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.

Channel number priority assignment apparatus

In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.

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Billerica, MA, United States of America

Elmer W Carroll