Digital Equipment Corporation

Elmer C Simmons

Michael D Leis

Russell W Brown

Bernardo Rub

Michael J Muchnik

Russell W Borwn

A multi-band processing system for automatically tuning the oscillator of a phase-locked loop to the frequency and phase of an applied input. The system includes an error detection circuit, a frequency controller, a scaling circuit, and a phase and frequency controller. The applied input and the oscillator output are coupled to the error detection circuit whose error output drives a charge pump/filter circuit. An error signal is derived from the difference between the loop charge pump output V.sub.1 and a preset charge pump zero error reference signal V.sub.ref, wherein the frequency controller regulates the oscillator output frequency according to a frequency error component of V.sub.1 -V.sub.ref, the scaling circuit scales the oscillator output frequency according to a system scaling signal N, and the phase and frequency controller adjusts the oscillator output frequency and phase according to V.sub.1 -V.sub.ref, when a 1/N multiple of the frequency of the oscillator output is compared in the error detection circuit to the frequency of the applied input.

Auto-centered phase-locked loop

A data decoding circuit which receives an input signal comprising a sequence of pulses and generates a digital data output signal and timing signals in response thereto. The circuit includes a phase-locked loop which generates timing signals in response to the input signal and an offset signal from a data separator circuit. The data separator circuit generates the digital data output signal and the offset signal, which measures the degree of correlation between the input signal as received by the data separator and the timing signal from the phase-locked loop, thereby obviating the need to match the data separator circuit closely to the phase-locked loop.

Data decoding circuit including phase-locked loop timing

A new differential amplifier circuit including two current mode logic circuits, each comprising a pair of transistors whose emitters are connected to a common current source. The differential amplifier circuit receives three input signals, with a transistor in both of the current mode logic circuits being controlled by one of the input signals. The collector outputs of the two transistors controlled by a single input signal are connected together, and the collector outputs of the two transistors controlled by the other two input signals are also connected together, in both cases to form summing junctions. The summing junctions are connected to an output buffer to generate a pair of signals constituting differential output signals.

Differential amplifier circuit

A circuit for filtering electrical waveforms in which the useful information is contained in patterns and spacing of zero-voltage crossings is disclosed. Illustratively, a disk memory system is disclosed in which the voltage peaks developed by the disk memory read-transducers are converted into zero-voltage crossing waveforms by differentiation. To eliminate false zero-voltage crossings caused by noise, the digital filter generates a linear ramp waveform whose magnitude is proportional to the time duration between successive zero-voltage crossings. False zero crossings typically have a short time duration between successive crossings. They are eliminated from the integrated ramp waveform by a comparator which only responds when the integrated waveform reaches a predetermined threshold level indicating the time between successive zero-voltage crossing exceeds a minimum time duration. A balanced version of the digital filter circuitry is also disclosed which recovers a limited, filtered version of the original zero-voltage crossing wave form except for a slight delay.

Growing community of inventors

Whitman, MA, United States of America

Elmer C Simmons