Sandisk Technologies Inc.

Elliott Peter Rill

Daniel Joseph Linnen

Kirubakaran Periyannan

The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nstage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nstage may include an Nfuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nelectronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal, and an Ndelay circuit coupled to the Ne-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Ne-fuse disconnecting. In this aspect, each of the stages of the failure event counting circuit may be configured to use the respective e-fuse to record a discrete failure event.

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San Jose, CA, United States of America

Elliott Peter Rill