Freescale Semiconductor,inc.

Ellen Y Lan

Bruce McRae Green

Charles E Weitzel

Olin L Hartin

Hsin-Hua P Li

Lawrence Scott Klingbeil

Matthias Passlack

Monte Gene Miller

Marcus R Ray

Randy D Redd

Philip Li

Phillip Li

Paul A Fisher

In one example embodiment, a transistor () is provided. The transistor () comprises a source (), a gate (), a drain (), and a field plate () located between the gate () and the drain (). The field plate () comprises a plurality of connection locations () and a plurality of electrical connectors () connecting said plurality of connection locations () to a potential.

Field plate transistor with reduced field plate resistance

In one embodiment, a semiconductor device () includes a buffer layer () formed over a substrate (). An AlGaAs layer () is formed over the buffer layer () and has a first doped region () formed therein. An InGaAs channel layer () is formed over the AlGaAs layer (). An AlGaAs layer () is formed over the InGaAs channel layer (), and the AlGaAs layer () has a second doped region formed therein. A GaAs layer () having a first recess is formed over the AlGaAs layer (). A control electrode () is formed over the AlGaAs layer (). A doped GaAs layer () is formed over the undoped GaAs layer () and on opposite sides of the control electrode () and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device () maintains linear operation over a wide temperature range.

pHEMT with barrier optimized for low temperature operation

A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

Recessed semiconductor device

In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (), a first dielectric layer () above the semiconductor substrate, a first ohmic contact region () and a second ohmic contact region () above the semiconductor substrate, a gate electrode () above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate () above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer () above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer () between the gate electrode and the field plate and not located above the gate electrode or the field plate.

Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate

A microwave field effect transistor () has a high conductivity gate () overlying a double heterojunction structure () that has an undoped channel layer (). The heterojunction structure overlies a substrate (). A recess layer that is a not intentionally doped (NID) layer () overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts () and permits significantly higher voltage operation than previous step gate transistors. Another recess layer () is used to define a gate dimension. A Schottky gate opening () is formed within a step gate opening () to create a step gate structure. A channel layer () material of InGaAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

Growing community of inventors

Chandler, AZ, United States of America

Ellen Y Lan