Cadence Design Systems, Inc.

Other

Ellen Sentovich

Andreas Kuehlmann

Christoph Albrecht

Philip Chong

Roberto Passerone

Luciano Lavagno

Kaushik Ravindran

A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Optimizing integrated circuit design through use of sequential timing information

Reducing critical cycle delay in an integrated circuit design through use of sequential slack

A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compliable. The designer specifies both computation and communication between different hybrid code modules.

Method and system for split-compiling a hybrid language program

Data path and placement optimization in an integrated circuit through use of sequential timing information

The present invention provides a process for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains. For the within domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound. Experiments have demonstrated that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock schedule.

Multi-domain clock skew scheduling

A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compilable. The designer specifies both computation and communication between different hybrid code modules.

Growing community of inventors

Oakland, CA, United States of America

Ellen Sentovich