Ambarella, Inc.

Ambarella International LP

Ellen M Lee

Leslie D Kohn

Peter Verplaetse

Yat Kuen Wong

Benghan Lui

An apparatus includes a memory and a hardware pipeline. The memory may be configured to store video data. The video data includes a plurality of sections of one or more pictures that may be processed independently. The hardware pipeline comprises a plurality of pipeline stages implementing a video coding process comprising a number of steps. Each of the plurality of pipeline stages performs an associated task of a different step of the video coding process in a substantially similar time on a different one of the plurality of sections as each of the plurality of sections pass through each of the pipeline stages. At least one of the plurality of pipeline stages communicates predictor information that is based on actual neighbor data to an earlier stage of the hardware pipeline.

Interleaved video coding pipeline

An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Memory access ordering for a transformation

An apparatus includes a circuit and a processor. The circuit may be configured to (i) generate a plurality of sets of coefficients by compressing a tile in a picture in a video signal at each of a plurality of different sizes of a plurality of coding units in a coding tree unit and (ii) reconstruct the tile based on a particular one of the sets of coefficients. The sets of coefficients may be generated at two or more of the different sizes of the coding units in parallel. Each of the sets of coefficients may be generated in a corresponding one of a plurality of pipelines that operate in parallel. Each of the sets of coefficients may have a same number of the coefficients. The processor may be configured to select the particular set of coefficients in response to the compression of the tile.

Tree-coded video compression with coupled pipelines

An apparatus includes a memory and a processor. The memory may be configured to store video data. The video data includes a plurality of sections of one or more pictures that can be processed independently. The processor generally includes a hardware pipeline. The hardware pipeline implements a number of stages of a video coding process, such that each stage performs an associated task in a substantially similar time on a different one of said plurality of sections.

An apparatus having a circuit and a processor is disclosed. The circuit may be configured to (i) generate a plurality of sets of coefficients by compressing a block in a picture in a video signal at a plurality of different sizes of coding units in a coding tree unit and (ii) generate an output signal by entropy encoding a particular one of the sets of coefficients. Each set of coefficients may be generated in a corresponding one of a plurality of pipelines that operate in parallel. The processor may be configured to select the particular set of coefficients in response to the compressing.

An apparatus comprising a decoder circuit, a memory circuit and a processing circuit. The decoder circuit may be configured to generate a first intermediate signal having a plurality of coefficients of a target layer and a plurality of coefficients of a base layer, in response to an input bitstream. The memory circuit may be configured to (i) store the first intermediate signal and (ii) present (a) a second intermediate signal comprising the plurality of coefficients of the target layer or (b) a third intermediate signal comprising the plurality of coefficients of the base layer. The processing circuit may be configured to (i) switch a plurality of times between the coefficients of the target layer and the coefficients of the base layer while reading a frame from the memory circuit, (ii) transform the coefficients of the base layer into base layer information, (iii) buffer the base layer information, where the base layer information buffered at any time comprises at most a subset of macroblock rows of the frame and (iv) generate an output signal comprising a plurality of target layer samples in response to the second intermediate signal and the base layer information as buffered.

Layer switching in an H.264 scalable video decoder

An apparatus comprising a transform circuit, a first coder circuit, a second coder circuit, and a memory circuit. The transform circuit may be configured to generate (i) one or more first coefficients in response to a sample signal when in a first mode and (ii) the sample signal in response to the first coefficients when in a second mode. The first coder circuit may be configured to generate (i) a first bitstream signal in response to one or more second coefficients when in the first mode and (ii) the second coefficients in response to the first bitstream signal when in the second mode. The second coder circuit may be configured to generate (i) a second bitstream signal in response to one or more third coefficients when in the first mode and (ii) the third coefficients in response to the second bitstream signal when in the second mode. The memory circuit may be configured to store the first coefficients, the second coefficients, and the third coefficients. The memory may be configured to allow the transform circuit, the first coder circuit, and the second coder circuit to operate independently.

Growing community of inventors

Saratoga, CA, United States of America

Ellen M Lee