Globalfoundries U.S. Inc.

Elizabeth Strehlow

David C Pritchard

Heng Yang

Hongru Ren

James Mazza

Manjunatha Govinda Prabhu

Neha Nayyar

Salvatore Cimino

Kai Sun

Anton Tokranov

Romain H A Feuillette

Yusheng Bian

Qizhi Liu

Judson Robert Holt

Hong Yu

Jia Zeng

Xuelian Zhu

Mohamed Rabie

Motoi Ichihashi

Jay A Mody

Bernhard J Wunder

Romain Feuillette

Harold Mendoza

Clynn J Mathew

Yea-Sen Lin

Structures with features formed by self-aligned double patterning and methods of self-aligned multiple patterning. The structure comprises a first field-effect transistor including a first gate and a first protrusion projecting laterally from the first gate, and a second field-effect transistor including a second gate and a second protrusion projecting laterally from the second gate. The second gate and the second protrusion are spaced in a lateral direction from the first gate and the first protrusion. The structure further comprises a gate contact connecting the first protrusion of the first gate to the second protrusion the second gate.

Self-aligned double patterning with mandrel manipulation

A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

Planar transistor device comprising at least one layer of a two-dimensional (2D) material

The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

Logic cell layout design for high density transistors

Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

Motion-sensitive field effect transistor, motion detection system, and method

Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.

Public-private encryption key generation using Pcell parameter values and on-chip physically unclonable function values

Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices

Structures for a grating coupler and methods of fabricating a structure for a grating coupler. The structure includes a grating coupler having a central portion and edge portions. The central portion and the edge portions define a sidewall, and the central portion and the edge portions have a first longitudinal axis along which the edge portions are arranged in a spaced relationship. Each edge portion projects from the sidewall at an angle relative to the first longitudinal axis. A waveguide core is optically coupled to the grating coupler. The first longitudinal axis is aligned in a first direction, and the waveguide core has a second longitudinal axis that is aligned in a second direction different from the first direction.

Angled grating couplers with inclined side edge portions

An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structure

An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

IC structure with single active region having different doping profile than set of active regions

One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

Vertical transistor device comprising a two-dimensional (2D) material positioned in a channel region of the device and methods of making such vertical transistor devices

One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

Growing community of inventors

Malta, NY, United States of America

Elizabeth Strehlow