Intel Corporation

Elizabeth M Kappler

Scott P Dubal

Patrick L Connor

Matthew A Jared

Duke C Hong

Chris Pavlas

Douglas Boom

Mark V Montecalvo

Ben-Zion Friedman

Ilango S Ganga

Sanjeev Jain

Brian J Skerry

Daniel Daly

Nrupal R Jani

John R Fastabend

Neerav Parikh

Calin Gherghe

Patrick Conner

Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

Many-to-many PCIE switch

Many-to-many PCIe switch

NUMA node peripheral switch

Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.

Device for indicating packet processing hints

Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.

Live migration of virtualized systems

Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.

NUMA aware network interface

Disclosed are exemplary embodiments for updating a networked machine having at least a dormant state and an active state. In various embodiments, when the machine it is a dormant state, it listens to a network for candidate updates, that is, updates that may be applicable to the machine. In some embodiments, determining the candidate update is an applicable update for the machine may be based at least in part on a variety of reasons, including testing if it has already been applied, does not actually update some aspect of the machine, conflicts with an existing configuration of the machine, conflicts with a policy of the machine, etc. The machine may cache some or all of the candidate updates or applicable updates, where a variety of rationales or policies may be used to control update retention. When the machine enters an active state, such as a power on or non-sleep mode, or other active state, the machine may validate integrity of an applicable update if not done while the machine was dormant, and optionally choose to install it.

Updating machines while disconnected from an update source

Techniques are described that can be used to identify a defective communication channel in a communications network. A decoder in a receiver may decode a signal received from a network. The decoded signal may be re-encoded and compared with the signal received from the network. A count of differences between the re-encoded signal and the signal received from a network may be provided. An indication of errors remaining after the decoding may also be provided. Based on the count and the indication, a defect in the communication channel may be identified. A user may be notified and/or actions may take place.

Techniques to determine transmission quality of a signal propagation medium

A method for preventing counterfeit of a hardware device is disclosed. The method comprises determining whether a first indicator for a hardware device is set, wherein the first indicator when set indicates that the device is not a counterfeit device, and if the first indicator is not set, then activating a counter, setting a second indicator when the counter expires, and operating the hardware device in a counterfeit mode when the second indicator is set, wherein the counterfeit mode identifies the hardware device as a counterfeit device. Other embodiments are also disclosed.

Mechanism to prevent counterfeiting in a hardware device

Corrupted configuration data stored in a first memory for a device may be restored using backup configuration data stored in a second memory. In one embodiment, the second memory may be carried by the device itself. In another embodiment, the second memory may be carried on a motherboard and may store backup configuration data for more than one device. Other embodiments are described and claimed.

Growing community of inventors

Hillsboro, OR, United States of America

Elizabeth M Kappler