Digital Equipment Corporation

Elizabeth M Cooper

Peter J Bannon

Michael Leary

A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.

High speed method for maintaining cache coherency in a multi-level, set

A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.

Growing community of inventors

Menlo Park, CA, United States of America

Elizabeth M Cooper