Pdf Solutions, Incorporated

Elizabeth Lagnese

Jonathan Haigh

Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.

Snap-to valid pattern system and method

The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same

Disclosed techniques conform standard cells in an integrated circuit design into a valid template pattern using a template-based approach to standard cell design. The template architecture stores valid patterns of circuit elements for the design. A Boolean expression comprising an aggregated set of Boolean assertions can be generated for each different combination of cell shape features and edge locations with the cell design to compute a solution that matches with a valid pattern in one of the templates. If the solution evaluates to a Boolean TRUE result, the cell shape(s) can be modified in accordance with the solution. If not, the granularity can be updated by incrementing an 'adjustment neighborhood' value and iterating the computations for shape features and edge locations using the updated values for the analysis until a Boolean TRUE result is found or it is determined there is no solution for the set of expressions.

Standard cell design conformance using boolean assertions

Described is a method for automatically determining proposed standard cell design conformance based upon template constraints.

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San Jose, CA, United States of America

Elizabeth Lagnese