Texas Instruments Corporation

Other

Elizabeth Costner Stewart

Jeffrey Alan West

Thomas Dyer Bonifield

Byron Lovell Williams

Jay Sung Chun

Zhiyi Yu

Ming-Yeh Chuang

Neng Jiang

Robert Lee Brown

Joseph Andre Gallegos

Ricky A Jackson

Nicholas Stephen Dellas

Adrian Salinas

Yung Shan Chang

Dhanoop Varghese

Young Sawk Oh

Thomas Dyer Bonifeld

An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.

Transistor with field plate over tapered trench isolation

An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.

Semiconductor wafer scribelane structure

An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Standalone isolation capacitor

A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Standalone high voltage galvanic isolation capacitors

An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

Integrated capacitor with sidewall having reduced roughness

Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

Passive components with improved characteristics

An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.

Hybrid high and low stress oxide embedded capacitor dielectric

Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

Method of fabricating a thick oxide feature on a semiconductor wafer

A method comprises obtaining a wafer comprising a plurality of components, wherein each of the plurality of components exposes a first surface of the component present in a first focal plane and a second surface of the component present in a second focal plane. The method comprises generating, by an optical tool, a first image of the first surface and a second image of the second surface of one of the plurality of components. The method comprises comparing, by a processor, the first image with a first reference image to produce a first value and the second image with a second reference image to produce a second value. The method comprises generating, by the processor, a wafer map indicating a quality state of the one of the plurality of components based on the first and second values.

Generating multi-focal defect maps using optical tools

An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.

Crack suppression structure for HV isolation component

A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.

An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

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Dallas, TX, United States of America

Elizabeth Costner Stewart