International Business Machines Corporation

Eliyahu Shamsaev

Israel A Wagner

Tibi Galambos

David Goren

Michael Zelikson

Jungwook Yang

Moshe Leibowitz

Yevgeny Perelman

Viktor Ariel

A method for converting a signal from analog-to-digital domain. Upon receipt of an i with triggering signal, where 1&lE;i&lE;N, the method includes initiating at least a partial AD operation. Upon completion of the at least partial operation, the method may includes generating and transmitting an i &plus;1 triggering signal. The i &plus;1 triggering signal may be adapted to initiate an i &plus;1 at least partial operation, thereby creating an asynchronous process. The method further includes repeating the above operations until completion of the analog to digital conversion. In some embodiments of the present invention, upon completion of the conversion, i&equals;N and the i &plus;1 operation is a power-down function.

Power-scalable asynchronous architecture for a wave-pipelined analog to digital converter

An analog-to-digital converter (ADC), including a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages. The ADC has a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.

Differential interpolated analog to digital converter

A switched capacitor circuit, including a load-capacitor, and a charging switch which is coupled to apply a potential to the load-capacitor. The circuit further includes a compensating-capacitor and switching circuitry which is coupled to the charging switch and the compensating-capacitor and which is switchable. The switching is arranged to transfer to the compensating-capacitor an injection error charge produced by the charging switch, and then to isolate the injection error charge on the compensating-capacitor from the load-capacitor.

Charge cancellation circuit for switched capacitor applications

An analog-to-digital converter, including a code generator, coupled to receive an input analog voltage and to one or more reference voltages, and adapted to generate a digital code responsive thereto, and one or more folded differential logic encoders (FDLEs) . Each of the FDLEs includes a plurality of capacitors and switching logic. The switching logic is coupled to receive the digital code and distribute a charge between the plurality of capacitors responsive to the received digital code, and to output a digital bit indicative of the input analog voltage responsive to a magnitude of a potential generated by the distributed charge on at least one of the plurality of capacitors.

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Haifa, Israel

Eliyahu Shamsaev