Qualcomm Incorporated

Other

Elisha John Ulmer

Richard Dominic Wietfeldt

Lalan Jee Mishra

John Hillan

Jeremy M Stein

Srinivas Maddali

Steven James Doerfler

Haggai Haim Haller

Xinghui Niu

Systems, methods, and apparatus for optimizing bus turnaround in a master-driven serial bus are described. A method performed at a master device coupled to a serial bus includes configuring slave devices coupled to the serial bus with respective delay values that define bus turnaround wait periods, transmitting a first read command directed to a first slave device, receiving data after a first wait period initiated after the first read command has been sent, the first wait period being defined by a delay value configured in the first slave device, transmitting a second read command directed to a second slave device, and receiving data after a second wait period initiated after the second read command has been sent, the second wait period being defined by a delay value configured in the second slave device. The first wait period and the second wait period may have different durations.

Configuring optimal bus turnaround cycles for master-driven serial buses

Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

Super-speed UART with pre-frame bit-rate and independent variable upstream and downstream rates

A method and apparatus for detecting the configuration of a device in a processing system are described. In one embodiment, a page size parameter associated with a memory device is identified. Further, one or more configuration parameters associated with the memory device are also identified, the page size parameter and the configuration parameters enabling access to the memory device. Finally, a request to download application data from the memory device based on the page size parameter and the one or more configuration parameters is transmitted to the memory device.

Hardware-assisted device configuration detection

Accessing memory on a first device from a second device is supported by reversible host/client interfacing between the devices. The reversible interfacing permits the first and second devices to be configured respectively as host and client, or respectively as client and host.

Remote memory access using reversible host/client interface

A method and apparatus for normalizing a plurality of state-metric registers in a decoder using a trellis. The method includes determining an approximate minimum of respective state-metric values stored in the plurality of state-metric registers, and subtracting the approximate minimum from the values. Determining the approximate minimum preferably includes determining the minimum of a predetermined number of most significant bits in the plurality of state-metric registers.

Efficient trellis state metric normalization

A read/write electronic memory bank 10, including a plurality of memory units 22-28 and 12-18 which receive a common clock signal having a repetitive clock cycle and have a common input port 20, 21 and a common output port 30, 31. The units function such that in each clock cycle an input word is written to the memory bank 10 from the input port 20, 21 and an output word is read from the memory bank 10 to the output port 30, 31. Each memory unit 22-28 and 12-18 includes a single-port random-access memory (RAM) device 22-28 and a first-in first-out (FIFO) buffer 12-18, such that when the output word is to be read from the same memory unit 22-28 and 12-18 to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port 20, 21, 30, 31 of the memory bank 10 and the FIFO buffer 12-18, instead of between the respective port 20, 21, 30, 31 of the memory bank 10 and the RAM device 22-28.

Growing community of inventors

Tiberias, Israel

Elisha John Ulmer