Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Institut National De La Sante Et De La Recherche Medicale

Université´ D'aix-marseille

Leland Stanford Junior University

Centre National De La Recherche Scientifique

Altis Semiconductor

Elisa Vianello

Michel Harrand

Gabriel Molas

Philippe Blaise

Laurent Grenouillet

Olivier Thomas

Raluca Tiron

Marios Barlas

Thomas Dalgaty

Faiz Dahmani

Selina La Barbera

Bastien Giraud

Olivier Bichler

Jean-Michel Portal

François Rummens

Tifenn Hirtzlin

Blaise Yvert

Benoît Sklenard

Binh Quang Le

Claire Fenouillet-Beranger

Gabriele Navarro

Subhasish Mitra

Jean-François Nodin

Bruno Fain

Jean Coignus

Alexandre Valentian

Thomas Cabout

Benoit Sklenard

Niccolo Castellani

Jean-Francois Nodin

Rémy Gassiloud

Etienne Nowak

Emmanuel Hardy

Rémy Gassilloud

Giorgio Palma

Catherine Carabasse

Marie Bernert

Thilo Werner

Thomas Mesquida

Alessandro Grossi

Michele Martemucci

Gaëlle Chamiot-Maitral

Fan Tony Wu

Djohan Bonnet

Eduardo Esmanhotto

Philip Wong

Cécile Nail

Joël Minguet Lopez

Benoït Sklenard

A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to the word line or the source line and having the same direction as the common bit line.

Hybrid FeRAM/OxRAM data storage circuit

A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M≥1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

Memory cell, electronic circuit comprising such cells, related programming method and multiplication and accumulation method

A method for co-manufacturing a FeRAM and an OxRAM includes depositing a layer of first electrode carried out identically for a zone Zand a zone Z; depositing a layer of hafnium dioxide-based active material carried out identically for Zand Z; depositing a first conductive layer carried out identically for Zand Z; making a mask at Z, leaving Zfree; removing the layer at Z, with Zbeing protected by the mask; removing the mask at Z; and depositing a second conductive layer in contact with the layer at Zand in contact with the layer at Z, the material of the layer being chosen to create oxygen vacancies in the active layer and depositing a third conductive layer carried out identically for Zand Z

Method for co-manufacturing a ferroelectric memory and an OxRAM resistive memory and device co-integrating a ferroelectric memory and an OxRAM resistive memory

A Bayesian neural network including an input layer, and, an output layer, and, possibly, one or more hidden layer(s). Each neuron of a layer is connected at its input with a plurality of synapses, the synapses of the plurality being implemented as a RRAM array constituted of cells, each column of the array being associated with a synapse and each row of the array being associated with an instance of the set of synaptic coefficients, the cells of a row of the RRAM being programmed during a SET operation with respective programming current intensities, the programming intensity of a cell being derived from the median value of a Gaussian component obtained by GMM decomposition into Gaussian components of the marginal posterior probability of the corresponding synaptic coefficient, once the BNN model has been trained on a training dataset.

Bayesian neural network with resistive memory hardware accelerator and method for programming the same

The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level.

Hybrid resistive memory

A method for training a logistic regression classifier on a dataset by using a resistive RAM as hardware accelerator, each row of the resistive RAM including cells which can be programmed in a first resistance state or a second resistance state. The probability of a data element belonging to a class is modelled by a logistic function applied to a score of the element, where is a parameter vector of the model. The logistic regression classifier is trained by populating the resistive RAM with samples of a model parameter vector which are obtained by MCMC sampling. Once populated, the resistive RAM can be used for classifying new data.

Method of training a logistic regression classifier with a resistive random access memory

Method for fabricating molds for lithography by nano-imprinting

A processing system for processing signals from a plurality of transducers of an ultrasonic sensor in order to determine characteristic information relating to an object detected by the ultrasonic sensor is provided. The system comprises a coupling device for transforming the signals received from the transducers into pulses, and a pulse processing unit for determining the characteristic information based on the pulses delivered by the coupling device. The coupling device comprises: a thresholding unit for applying, for each signal received from a transducer, thresholding to a signal derived from the signal received from the transducer and extracting directional information contained in the phase of the derived signal; a transformation unit for transforming the derived signal into pulses containing the phase of the signal, using the information extracted by the thresholding unit.

Device and method for processing signals from a set of ultrasonic transducers

A modulation device includes at least one memristive device, and a control block, the modulation device having an equivalent conductance y(t) produced by the at least one memristive device and the control block being configured to receive a clock signal and perform a first modification of the equivalent conductance y(t) upon receipt of each clock signal, receive an input voltage pulse and perform a second modification of the equivalent conductance y(t) upon receipt of each input voltage pulse, the first and second modifications being in opposite directions.

Modulation device and method, artificial synapse comprising said modulation device, short term plasticity method in an artificial neural network comprising said artificial synapse

A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.

Method of producing a recurrent neural network computer

A method for unsupervised sorting, in real time, of action potentials of biological neurons by a network of artificial neurons including input, intermediate and output layers, the method according to which: the input layer receives an electrical signal measuring an electrical activity of biological neurons, the electrical signal having a variable amplitude as a function of action potentials emitted by the plurality of biological neurons over time; the input layer converts the amplitude of the electrical signal into a train of first spikes; the input layer transmits the train of first spikes to the intermediate layer; the intermediate layer converts the train of first spikes into a train of second spikes; the intermediate layer transmits the train of second spikes to the output layer; as a function of the train of second spikes, the output layer sorts each occurrence of each type of action potential present in the electrical signal.

Method for unsupervised sorting in real time of action potentials of a plurality of biological neurons

The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Circuit and method for programming resistive memory cells

A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: &#x2014;a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and&#x2014;a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.

Oxide-based resistive non-volatile memory cell and method for manufacturing same

A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

Resistive random access memory device

A programming method for an artificial neuron network having synapses, each including a single resistive random-access memory having first and second electrodes on either side of an active zone, the method including determining a number N of conductance intervals, where N&#x2265;3; for each memory: choosing a conductance interval from amongst the N intervals; a step i) for application of a voltage pulse of a first type between the first and second electrodes, and for reading the conductance value of the memory; if the conductance value does not belong to the previously chosen conductance interval, a sub-step ii) for application of a voltage pulse of a second type between the first and second electrodes, and for reading the conductance value; if the conductance value does not belong to the chosen conductance interval, a step according to which step i) is reiterated, with steps i) and ii) being repeated until the conductance value belongs to the interval.

Method of programming an artificial neuron network

Growing community of inventors

Grenoble, France

Elisa Vianello