Platina Systems Corporation

Cisco Technology, Inc.

Eliot Michael Dresselhaus

Dino Farinacci

Jason Luo Pang

Mark Tehmin Yin

Frank Szu-Jen Yang

Andreas Demetrios Bovopoulos

David Richard Barach

In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.

Heterogeneous network in a modular chassis

An intermediate network node is configured to forward a plurality of packets concurrently, e.g., as a vector, rather than one packet at a time. As such, the node can load a single sequence of forwarding instructions that may be repeatedly executed for packets in the vector. In addition, the intermediate network node adaptively controls the rate at which it processes data packets through a directed forwarding graph. To that end, the intermediate node is configured to dynamically select the number of packets per vector, i.e., vector size, processed at each node of the forwarding graph. Further, the intermediate node also may be configured to dynamically select timing intervals for one or more 'node timers' used to control the rate at which packets traverse through the graph. Illustratively, the vector size and node-timer intervals are selected so that the average latency through the forwarding graph is less than a predetermined target latency, e.g., 50 microseconds (&#x3bc;s).

Vectorized software packet forwarding

Growing community of inventors

San Francisco, CA, United States of America

Eliot Michael Dresselhaus