Novellus Systems Incorporated

Signetics

National Semiconductor Corporation

North American Philips Corp, Signetics Division

Other

Siliconix Incorporated

Eliot K Broadbent

Jeffrey C Benzing

Barry Lee Chin

Christopher William Burkhart

Everhardus P Van De Ven

Evan E Patton

Steven T Mayer

Jonathan David Reid

Robert J Contolini

Edward C Opocensky

Theodore Cacouris

Lawrence C Lane

Michael E Thomas

Kenneth C Miller

J Kirkwood Rough

Edward J McInerney

Everhardus P Van De Van

Robert T Rozbicki

Michal Danek

John Stephen Drewery

Erich R Klawuhn

Karl B Levy

Ronald Allan Powell

Jeffrey A Tobin

Mukul Khosla

J Kirkwood H Rough

Kirkwood H Rough

Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.

Sequential station tool for wet processing of semiconductor wafers

The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.

Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation

The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

Passivation of copper in dual damascene metalization

An induction plasma source for integrated circuit fabrication includes an induction coil which defines a generally convex surface. The convex surface may be in the form of a spherical section less than a hemisphere, a paraboloid, or some other smooth convex surface. The windings of the induction coil may be spaced at different intervals in different sections of the coil and may be in multiple layers in at least a portion of the coil. Varying the shape of the coil and the distribution of the coil windings allows the plasma to be shaped in a desired manner.

Plasma process apparatus for integrated circuit fabrication having dome-shaped induction coil

In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called 'terminal effect', the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.

Method of electroplating semiconductor wafer using variable currents and

Method of electroplating semicoductor wafer using variable currents and

An electroplating system includes shield(s) to control the thickness profile of a metal electrodeposited onto a substrate. The shield(s) are positioned between the anode and the cathode in a standard electroplating apparatus with a device for rotating the plating surface. The cathode is rotated so that the shield(s) in conjunction with the rotation of the cathode selectively alters or modulates a time average of the electric field characteristics between the anode and the cathode. The modulated electric field is used to control the electrodeposition rate at selected area(s) of the plating surface of the cathode, thereby causing the metal deposited on the cathode to have a modified thickness profile.

Electroplating system with shields for varying thickness profile of

A platen supports a substrate on an interior platen region during the deposition of materials such as tungsten, metal nitrides, other metals, and silicides in a chemical vapor deposition ('CVD') reactor. A deposition control gas composed of a suitable inert gas such as argon or a mixture of inert and reactive gases such as argon and hydrogen is introduced into the CVD reactor. Deposition control gas is preferably introduced through a restrictive opening in a gas orifice surrounding the platen interior region and exits near an edge of the substrate. The restrictive opening accommodates a uniform deposition control gas flow proximate to an edge of the substrate at a pressure greater than reactor pressure near the substrate edge. The deposition control gas substantially prevents process gas access to the substrate edge and backside. In one embodiment, the restrictive opening is formed by placing a restrictive insert within a gas groove surrounding the platen interior region. In another embodiment, the restrictive opening is formed by an exclusion guard substantially uniformly spaced from the edge of the substrate.

Gas-based substrate deposition protection

A platen supports a wafer during the deposition of tungsten, metal nitrides, other metals, and silicides in a chemicalvapor deposition reactor. A deposition control gas that includes a suitable inert gas such as argon or a mixture of inert and reactant gases such as argon and hydrogen is introduced through a restrictive opening into an ambient in the reactor. An exclusion guard aligned with the platen has an extension extending over a frontside peripheral region of the wafer. Deposition control gas is introduced under the exclusion guard extension and exits through a restrictive opening between the exclusion guard extension and a wafer frontside peripheral region. The restrictive opening provides a uniform pressure of deposition control gas at the edge and frontside of the wafer to prevent deposition on the wafer edge and backside.

Apparatus for preventing deposition on frontside peripheral region and

A platen supports a wafer during the deposition of tungsten, metal nitrides, other metals, and silicides in a chemical vapor deposition reactor. A deposition control gas that includes a suitable inert gas such as argon or a mixture of inert and reactant gases such as argon and hydrogen is introduced through a restrictive opening into an ambient in the reactor. An exclusion guard aligned with the platen has an extension extending over a frontside peripheral region of the wafer. Deposition control gas is introduced under the exclusion guard extension and exits through a restrictive opening between the exclusion guard extension and a wafer frontside peripheral region. The restrictive opening provides a uniform pressure of deposition control gas at the edge and frontside of the wafer to prevent deposition on the wafer edge and backside.

Exclusion guard and gas-based substrate protection for chemical vapor

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San Jose, CA, United States of America

Eliot K Broadbent