Micron Technology Incorporated

Elio D'Ambrosio

Pasquale Pistilli

Giulio-Giuseppe Marotta

Giovanni Naso

Dionisio Minopoli

Pietro Piersimoni

Ciro Chiacchio

Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.

Method and apparatuses for managing double data rate in non-volatile memory

An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

Enhanced protection for input buffers of low-voltage flash memories

A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.

Multiple partition memory command user interface

A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Command user interface with programmable decoder

Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

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Avezzano, Italy

Elio D'Ambrosio