Motorola Corporation

Broadcom Corporation

Broadlight Ltd.

Avago Technologies International Sales Pte. Limited

Freescale Semiconductor,inc.

Eliezer Weitz

Gal Sitton

Asaf Koren

Moti Kurnick

Yoram Yeivin

Ifat Naaman

Gil Levy

Eli Elmoalem

David Avishai

Avi Hagai

Yariv Aviram

Avi Shalev

Ryan E Hirth

Adi Katz

Amiad Dvir

Moshe Tarrab

Alex Goldstein

Raanan Gewirtzman

Michael Balter

Yehuda Rudin

Yehuda Shaik

Igor Elkanovich

Boaz Shachar

Ira Joffe

Mitchell Gordon McGee

Oren Issac Wolach

Yoram Gorsetman

Igor Ternovsky

Daniel Pasternak

Assaf Amitai

Hilla Ben Yaacov

Yeivin Yoram

Jacob Harel

Alexander Goldstein

Noam Sheffer

Bela Federmesser

Raphael Paul Claude André Cassiers

Benoit Marcel Simon Christiaens

Koby Harel

Rozen Nahum

Ronen Amrani

Tal Baum-Mizrachi

Yanai Pomeranz

Yossi Socoletzki

Yehiel Engel

An example traffic management system for a network device includes: a first memory storing queues of packets received by the network device; a second memory storing data of a scheduler for the queues that schedules transmission of the packets to a port of the network device; and an accelerator circuit including a third memory to store a data structure, the accelerator circuit coupled to the second memory and operable to: load, for a first iteration of a traverse operation in response to a command, a field of the data structure in the third memory with data from a first node of the scheduler; update, during the first iteration of the traverse operation, the field of the data structure in the third memory; and store, during the first iteration of the traverse operation, updated data from the field to the first node in the second memory.

Traffic management in a network device

The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Network processors

An optical line terminal (OLT) is operable in a passive optical network (PON). The OLT comprises a plurality of optical network units (ONUs), an electrical module for generating continuous downstream signal and processing received upstream burst signals according to a communication protocol of the PON and an optical module for transmitting continuous optical signals over a first wavelength and receiving burst optical signals over a second wavelength. The optical module further includes an ONU traffic processing module is electrically coupled to the optical module and the electrical module. The ONU traffic processing module is configured to emulate one of the ONUs of the PON. An interface is used for interfacing between the electrical module and the optical module.

Optical line terminal (OLT) optical module adapted to perform optical unit network (ONU) functionality

A passive optical network (PON) packet processor for processing PON traffic includes a core processor for executing threads related to the processing of PON traffic and a plurality of hardware (HW) accelerators coupled to the core processor for accelerating the processing of said PON traffic. A memory unit is coupled to the core processor for maintaining program and traffic data. In an embodiment of the present invention, the PON packet processor includes a scheduler that optimizes the execution of PON related tasks.

Passive optical network (PON) packet processor

A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).

Enhanced passive optical network (PON) processor

A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.

Network processor for supporting residential gateway applications

A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.

Passive optical network processor with a programmable data path

A gigabit passive optical network (GPON) residential gateway comprising a microprocessor for at least processing packets including voice data and packets including video data; dual packet processors for performing GPON and residential gateway processing tasks; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices; a GPON MAC adapter for interfacing with an optical line terminal (OLT) of the GPON; and a digital signal processor (DSP) for processing voice signals.

Gigabit passive optical network (GPON) residential gateway

An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).

An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

High-speed internal bus architecture for an integrated circuit

A communication controller ( ) for handling and processing data packets received from a large number of communication channels ( ). The communication controller ( ) comprising of: a processor ( ) for processing data; a serial interface ( ), coupled to the communication channels ( ). A multi channel controller ( &prime;) coupled to the serial interface ( ) and the processor ( ), for interfacing between the communication channels ( ) and the processor ( ). The communication channels ( ) and the serial interface ( ) send and receive data packets. The processor ( ) sends, receives and processes data words. The multi channel controller ( ) receives data packets from the serial interface ( ), concatenates data packets and sends data words to the processor ( ). The multi channel controller ( ) receives data words from the processor ( ), and transmits data packets to the serial interface ( ).

Multi channel controller

A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.

High performance communication controller for processing high speed data streams wherein execution of a task can be skipped if it involves fetching information from external memory bank

A communication system (100) comprises a processor (150), a channel memory (160), a communication line (180), a transmit connect table (146), a transmit scheduler table (144), and a program memory (148). The channel memory (160) stores channels (161) with data cells (102). The processor (150) writes channel identifiers (e.g., 1 2) into schedule fields (110-V) of the transmit scheduler table (144) and points with a pointer R and a pointer V to the schedule fields (110-V). The pointers R and V identify fields in which the processor (150) looks up for a first channel identifier. The processor (150) forwards data cells (102) from the channel memory (160) to the communication line (180) for the channel (161) corresponding to the first channel identifiers. Then, the processor (150) moves the first channel identifier to an other field and writes a second channel identifier stored in the transmit connect table (146) to the field of the first channel identifier.

Apparatus and method for transmitting data

A data communication system (2) provides a circuit and method for prioritizing and controlling the transfer of data to and from a plurality of communication channels (6-11). The data communication system defines a predetermined data threshold level (X,Y) for a data buffer (16-21) for each of the plurality of communication channels. A service request signal is generated for a one of the plurality of communication channels when a respective data buffer stores data to be transferred. The data communication system generates a threshold signal for a communication channel when a data value stored in a respective data buffer reaches a predetermined data threshold level of the data buffer. The priority levels of the communication channels which generate threshold and service request signals are then compared to determine a high priority communication channel. The highest priority communication channel is then serviced.

Data communication system for controlling prioritization and transfer of

A high speed multichannel HDLC framing machine (112) cycles through Time Division Multiplexed (TDM) channels identifying a channel table (188) for each channel. HDLC state, data to be framed, and a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer (112) returns an updated HDLC state, status flags, and a framed code word. The framed code word is multiplexed in a FIFO queue (58) for output on the high speed TDM line (28). A high speed multichannel HDLC deframing machine (112) receives a series of code words from a FIFO queue (56). For each code word received, a corresponding channel table (188) is identified. HDLC state, the code word to be deframed and, a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer returns an updated HDLC state, status flags, and potentially a deframed data word.

Multichannel HDLC framing/deframing machine

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Holon, Israel

Eliezer Weitz