Intel Corporation

Tahoe Research, Ltd.

Eliezer Weissmann

Efraim Rotem

Doron Rajwan

Alon Naveh

Nadav Shulman

Nir Rosenzweig

Avinash N Ananthakrishnan

Ohad Falik

Ilan Pardo

Boris Ginzburg

Guy M Therien

Yoni Aizik

Michael Mishaeli

Hisham Abu Salah

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Mark B Rosenbluth

Ronny Ronen

Jasmin Ajanovic

Scott Dion Rodgers

Anil Vasudevan

Prashant Sethi

Sridhar Muthrasanallur

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Krishnakanth Venkata Sistla

Paul S Diefenbaugh

Russell Jerome Fenger

Anil Aggarwal

Jeremy J Shrall

Eugene Gorbatov

Robert Valentine

Andrew D Henroid

Jason W Brandt

Ankush Varma

Inder M Sodhi

Ryan Donovan Wells

David A Koufaty

Dheeraj R Subbareddy

Ganapati Srinivasa

Scott D Hahn

Paolo L Narvaez

Dorit Shapira

Yuval Yosef

James B Crossland

Avi Mendelson

Stephen H Gunther

Andrew J Herdrich

Alexander Gendler

Ben-Zion Friedman

Oren Ben-Kiki

Barnes Cooper

Eric DiStefano

Ahmad Yasin

Ian M Steiner

Rajshree Chabukswar

Tal Kuzi

Gilbert A Neiger

Mark Jay Charney

Eric C Samson

James G Hermerding, Ii

Jacob Doweck

Julius Yuli Mandelblat

Gal Leibovich

Nikhil Gupta

Bret L Toll

Ravishankar Iyer

Gad Shlomo Sheaffer

Stephen Anthony Fischer

Vivek Garg

Robert E Gough

Vasudevan Srinivasan

Ehud Cohen

Ashish V Choubal

Michael W Chynoweth

Hisham Shafi

Toby Opferman

Rinat Rappoport

Michael A Rothman

Mohan J Kumar

Ittai Anati

Koichi Yamada

Wei Ey Li

Dan Baum

Bryant E Bigbee

Sarathy Jayakumar

Asit K Mallick

Mark Doran

Lily Pao Looi

Konstantin Levit-Gurevich

Robert L Farrell

Jose Andy Vargas

Michael Zelikson

Aamer Jaleel

Douglas Raymond Moran

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling.

Device, method and system to provide thread scheduling hints to a software process

In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Multi-level loops for computer processor control

In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Processor having accelerated user responsiveness in constrained environment

A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

System, apparatus and method for loose lock-step redundancy power management

Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

Performance monitoring in heterogeneous systems

Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Apparatuses, methods, and systems for hardware control of processor performance levels

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Apparatus and method for dynamic control of microprocessor configuration

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

Application priority based power management for a computer device

The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

Methods of hardware and software-coordinated opt-in to advanced features on hetero ISA platforms

Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

Multi-level CPU high current protection

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

Growing community of inventors

Haifa, Israel

Eliezer Weissmann