Intel Corporation

Broadcom Corporation

Tahoe Research, Ltd.

Broadcom Israel Research, Ltd.

Mcafee, Inc.

Eliezer Tamir

Ben-Zion Friedman

Eliel Louzoun

Andrew Cunningham

Theodore L Willke

Shay Mizrachi

Phil C Cayton

Andrey Chilikin

Rafi Shalom

Eliezer Aloni

Dov Hirshfeld

Matthew R Wilcox

Aviv Greenberg

Assaf Grunfeld

Guy Corem

Ori Hanegbi

Anil Vasudevan

Vadim Makhervaks

Donald Wood

Jesse C Brandeburg

Peter P Waskiewicz, Jr

John Joseph Browne

Steven Bernard McGowan

Robert O Sharp

Bruce Richardson

Changzheng Wei

David Hunt

Niall Power

Scott P Dubal

Chris MacNamara

Stephen T Palermo

Frank L Berry

Niall D McDonnell

Itamar Fredi Levin

James Robert Hearn

Johannes Berg

Kevin Devey

Uri Tal

Jonas Svennebring

Miles J Penner

Steen K Larsen

Christopher MacNamara

Chris Pavlas

Vladislav Kopzon

Ygdal Naouri

Bjorn Topel

Carl-Oscar Montelius

Radia Joy Perlman

Kapil Sood

Hormuzd M Khosravi

Patrick L Connor

Arvind Srinivasan

Igor G Muttik

Alex Nayshtut

Ohad Falik

Men Long

Vadim Sukhomlinov

Anders Grunnet-Jepsen

Robert W Strong

Yadong Li

Lokpraveen B Mosur

Anjali Singhai Jain

Ilango S Ganga

James T Doyle

Manasi Deval

Iosif Gasparakis

Paritosh Saxena

Nicholas D Triantafillou

Andreas Kleen

Simoni Ben-Michael

Nrupal R Jani

Paul J Thadikaran

Akshay Ramesh Kadam

Prafulla Deuskar

Hari K Tadepalli

Eoin Walsh

Sean Harte

Krishnamurthy Jambur Sathyanarayana

Paul S Schmitz

Chris Macnamara

Edward J Pullin

Boris Kleiman

Itamar Levin

Nemanja Marjanovic

Rory Sexton

Richard J Heiler

Thomas Long

Eliel Louzon

Brad W Stewart

Carol L Barrett

Akeem Abodunrin

Lev Faerman

Suyog Kulkarni

Alexey Puzhevich

Shai Krigman

Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

Systems and methods for multi-architecture computing

Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.

Extending Berkeley packet filter semantics for hardware offloads

Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

Flow based rate limit

Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

Technologies for providing efficient detection of idle poll loops

Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Packet processing with reduced latency

Examples are disclosed for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may allocate, in a memory of the server, a buffer, a doorbell, and a queue pair accessible to a client remote to the server. For these examples, the network input/output device may assign an Non-Volatile Memory Express (NVMe) namespace context to the client. For these examples, indications of the allocated buffer, doorbell, queue pair, and namespace context may be transmitted to the client. Other examples are described and claimed.

Techniques for command validation for access to a storage device by a remote client

Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

Software-defined networking data re-direction

Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.

Virtual machine migration while maintaining live network links

Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.

Technologies for control plane separation in a network interface controller

Scalable techniques for data transfer between virtual machines (VMs) are described. In an example embodiment, an apparatus may include circuitry and memory storing instructions for execution by the circuitry to assign each one of a plurality of shared virtual memory spaces to a respective one of a plurality of virtual machines, wherein a first shared virtual memory space of the plurality of shared virtual memory spaces is assigned to a first virtual machine of the plurality of virtual machines, write, by the first virtual machine to the first shared virtual memory space, data to be provided to a second virtual machine of the plurality of virtual machines, and read, by the second virtual machine, the data in the first shared virtual memory space.

Scalable techniques for data transfer between virtual machines

Extending Berkeley Packet Filter semantics for hardware offloads

Extending berkeley packet filter semantics for hardware offloads

Growing community of inventors

Bait Shemesh, Israel

Eliezer Tamir