Bell Telephone Laboratories

At&t Bell Laboratories

Eliezer Kinsbron

William T Lynch

Frederick Vratny

Hyman J Levinstein

David B Fraser

Joshua Alspector

Thomas E Smith

William E Willenbrock, Jr

Marek A Sternheim

A method of fabricating field effect transistors which includes control of threshold potential by an ion implantation limited to the active channel area. The active channel area is defined by a photoresist pattern. Ions are implanted into the exposed area in a concentration to achieve a desired threshold. Appropriate metals are deposited over the channel area to form a gate electrode. The photoresist is lifted off leaving the gate electrode in position over the channel area. If desired, a layer of polysilicon can be included prior to resist formation and later removed by an etchant which does not attack the gate electrode.

Fabrication of FETs

A method for forming a shallow and highly concentrated arsenic doped surface layer in a silicon bulk region includes the steps of forming an arsenic doped polysilicon layer in contact with a preselected area of a bulk region surface in which the surface layer is to be formed and completely oxidizing the polysilicon layer at a rate exceeding the rate at which arsenic diffuses in the bulk region. Since arsenic has a relatively high silicon/silicon dioxide segregation coefficient and the oxidation rate exceeds the arsenic diffusion rate, arsenic accumulates at the silicon dioxide/silicon interface during oxidation, and nearly all of the arsenic in the region of the polysilicon layer above the preselected area is driven into the bulk region surface by the oxidation to form an impurity layer having a very high surface concentration of arsenic.

Method for fabricating a semiconductor device

An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.

Method for manufacturing an insulated gate field effect transistor device

Polyoxide capacitors for semiconductor integrated circuits having oxide dielectric films of 500 Angstroms or less are fabricated using in-situ doped polysilicon layers to have electrical field breakdowns of from 6 to 9 MV/cm. The first polysilicon layer is formed by LPCVD using silane and phosphine at a temperature in the range from about 570 degrees C. to 595 degrees C. These capacitors are relatively precisely valued devices used particularly in applications such as filter/codecs. However, they are useful wherever integral capacitors are needed having high dielectric strength polyoxides, including such semiconductor integrated circuit devices as EPROMs and dynamic RAMs.

Semiconductor integrated circuit capacitor

This invention involves the defining of a submicron feature (21 or 93) in a structure, typically an insulated gate field effect transistor structure (30, 40, or 110). This feature is defined by a sidewall oxide protective masking layer (21 or 71) formed by reactive oxygen ion etching of the structure being built at a time when an exposed surface thereof in the vicinity of the sidewall contains atoms of a material--for example, silicon or aluminum--which combine with the oxygen ions to form the sidewall oxide layer.

Formation of sidewall oxide layers by reactive oxygen ion etching to

It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.

Method of fabricating high-conductivity silicide-on-polysilicon

In an integrated circuit fabrication sequence, a hardened mask pattern adhered to an underlying substrate is removed from the substrate by a solvent that comprises anhydrous hydrazine and dimethyl sulfoxide. The solvent rapidly penetrates the interface between the pattern and the underlying substrate and quickly breaks the adhesive bonds therebetween. Other materials (e.g., Al, Si, SiO.sub.2) in the structure being fabricated are not deleteriously affected by the solvent.

Removing hardened organic materials during fabrication of integrated

In the patterning of an organic layer on a VLSI wafer by means of reactive oxygen (or other) ion anisotropic etching, build-ups of oxides (or other compounds) on the sidewalls of apertures formed in the organic layer are removed prior to etching the material, typically aluminum, of the VLSI wafer located at the bottom of these apertures, using the patterned organic layer as an etch mask.

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Highland Park, NJ, United States of America

Eliezer Kinsbron