International Business Machines Corporation

Elie Awad

Mariette Awad

Kai D Feng

John Jay Maloney

Paul Joseph Panaccione

Sebastian Theodore Ventrone

Adam E Trojanowski

A system and method for protecting computing systems, and more particularly a system and method which a dedicated hardware component configured to communicate with a protection program. A computer hardware subsystem includes a memory comprising content. The content is at least a list of files which have been modified within a predetermined period of time. The list of files is a subset of files of a hard drive. A dedicated hardware component is configured to track the files which have been modified and provide a location of the files to the memory. A communication link between the dedicated hardware component and a protection program provides the protection program with the subset of files of the hard drive as referenced by the memory content.

System and method to protect computing systems

A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.

Design structure for compensating for variances of a buried resistor in an integrated circuit

A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor.

Method of generating a functional design structure

An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction.

Heatplates for heatsink attachment for semiconductor chips

A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.

Design of BEOL patterns to reduce the stresses on structures below chip bondpads

A method and apparatus that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.

Method and apparatus for compensating for variances of a buried resistor in an integrated circuit

An apparatus for heatsink attachment. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction.

A chip package is formed which has an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another to permit a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

Method for forming a chip package

Design of beol patterns to reduce the stresses on structures below chip bondpads

An electronic package for use with a printed circuit board is provided. The electronic package includes a ground layer having an upper and lower section, a semiconductor chip, a conductive signal layer and a ground plane having a first section electrically connected to the upper section of the ground layer and a second section substantially planar with said lower section of said ground layer, the second section of the ground plane having an additional area to prevent cracking of a solder connection between the ground layer, the ground plane and the printed circuit board.

Optimized electronic package

A chip package having an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another. Such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggering in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

Growing community of inventors

Essex Junction, VT, United States of America

Elie Awad