Motorola Corporation

Eliav Zipper

Michael Zarubinsky

Yachin Afek

Leonid Tsukerman

David Moshe

Konstantin Berman

A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref&equals;(Fmin&plus;Fmax)/2.

Phase lock loop having a robust bandwidth and a calibration method thereof

A signal generator ( ) receives an input clock signal (X ) at a first frequency (F ) and derives an output clock signal (Y) at a second frequency (F ). An arrangement ( ) using a first intermediate signal (Z) receives the input clock signal (X ) and provides a second intermediate signal (X ) by selectively providing transitions ( ) of the second intermediate signal (X ) at time intervals (T (n)) that are determined by a variable number (A&plus;P(n)) of periods (T ) of the first intermediate signal (Z). The second intermediate signal (X ) has a frequency (F ) that is in average (F&prime; ) higher than the first frequency (F ). A phase-looked loop (PLL) circuit ( ) locks at this average frequency (F&prime; ) and provides the output clock signal (Y).

Signal generator, and method

A buffer stage for buffering an input signal generated by a current controlled oscillator comprising: an input terminal that receives the input signal, an output terminal that outputs a buffered signal, at least one buffer, coupled between the input and output terminals that buffers the input signal to generate the buffered signal, the at least one buffer having a current control terminal; and at least one current source having an output coupled to the current control terminal of the at least one buffer, the at least one current source further including at least one control terminal that receives a buffer control signal so that the current output from the current source substantially equals the current sourced by the at least one buffer.

Output buffer stage for use with a current controlled oscillator

A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.

Low jitter phase locked loop having a sigma delta modulator and a method thereof

A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.

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Ramat Gan, Israel

Eliav Zipper