Cadence Design Systems, Inc.

Neolinear, Inc.

Elias Lee Fallon

Wangyang Zhang

Regis R Colwell

Hua Luo

Rob A Rutenbar

Sheng Qian

Hui Xu

Namita Bhushan Rane

David Allan White

Roland Ruehl

Hongzhou Liu

Henry K Yu

Harindranath Parameswaran

Sanjib Ghosh

Yinnie Lee

Joshua Alexander Baudhuin

Pardeep Juneja

Timothy Rosek

Harsh Deshmane

Anjna Khanna

Simon Simonian

Prakash Gopalakrishnan

Prakash Krishnan

Supriya Ananthram

Sai Bhushan

Shang Li

Weifu Li

Chirag Ahuja

Jose A Martinez

Saleha Khatun

Zhigang Wang

Donald B Reaves

Rong Chang Yan

Weiyi Qi

The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

System, method, and computer program product for analog and mix-signal circuit placement

The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.

System, method, and computer program product for predicting parasitics in an electronic design

A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.

System and method for device mismatch contribution computation for non-continuous circuit outputs

The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.

System, method, and computer program product for analog structure prediction associated with an electronic design

The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.

System, method, and computer program product for genetic routing in an electronic circuit design

The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should be grouped together.

System, method, and computer program product for group and isolation prediction using machine learning and applications in analog placement and sizing

The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.

System, method, and computer program product for the integration of machine learning predictors in an automatic placement associated with an electronic design

The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.

System, method and computer program product for automatic generation of sizing constraints by reusing existing electronic designs

The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.

System, method, and computer program product for optimization in an electronic design

Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.

Method and system for performing cross-validation for model-based layout recommendations

Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.

Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations

Disclosed is a method and system for translating parameterized cells (pcells) that are created using different programming languages. The pcell source code created in a first programming language undergoes a translation process to translate that source code to a second programming language. A validation process is also provided to ensure the correctness of the translations.

Method and system for implementing translations of parameterized cells

Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.

Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints

Disclosed are methods, systems, and articles of manufacture for implementing multi-scenario physically-aware design of electronic circuit design(s). In some embodiments, the method captures layout dependent effect(s) when a critical component instance, which corresponds to multiple candidate configurations, is being created in a physical design to enable a designer to create partial layout(s) from layout alternative(s) and to extract parameter(s) from the partial layout(s) in different layout contexts. The method may extract parasitics between components and analyzes impact(s) of layout dependent effect(s) on an electronic design by performing simulation(s) with layout dependent effect(s) in the schematic domain and may perform some partial routing based on some routing style(s) in each of the different layout contexts to generate just enough interconnects that may affect the electronic design.

Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects

Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.

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Allison Park, PA, United States of America

Elias Lee Fallon