Qualcomm Incorporated

Skyworks Solutions, Inc.

Motorola Corporation

Ditrans Ip, Inc.

Elias Dagher

Dinesh Jagannath Alladi

Lei Sun

Yan Wang

Seyed Arash Mirhaj

Yuhua Guo

Aram Akhavan

Dmitriy Rozenblit

Behnam Sedighi

Kentaro Yamamoto

Kevin Juan

Man H Ku

Tao Luo

Igor Gutman

Jeremy Darren Dunworth

Lai Kan Leung

Matthew Richard Miller

Timothy Donald Gathman

Omid Rajaee

Ganesh Kiran

Chieh-Yu Hsieh

Wesley K Masenten

Masoud Ensafdaran

Mohammad Meysam Zargham

Balasubramanian Sivakumar

Anand Meruva

Yongjian Tang

Keith Soo Hoo

Peter Stubberud

Thang Victor Dinh

Shi Bu

A system includes a switch transistor, and a bootstrap circuit having an input and an output, wherein the output of the bootstrap circuit is coupled to a gate of the switch transistor. The system also includes a first buffer having an input and an output, wherein the output of the first buffer is coupled to a terminal of the switch transistor. The system further includes a second buffer having an input and an output, wherein the input of the second buffer is coupled to the input of the first buffer, and the output of the second buffer is coupled to the input of the bootstrap circuit.

Kickback reduction in bootstrapped switches

Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

Noise shaping in multi-stage analog-to-digital converters

Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

Dynamic range adjustment for analog-to-digital converter (ADC)

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

Gain stabilization

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

Pipelined analog-to-digital conversion

An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

Analog-to-digital conversion

A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

Time-interleaved charge sampler receiver

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

Calibration for time-interleaved analog-to-digital converters and signal generators therefor

A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

Continuous-time analog-to-digital converter

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

Continuous-time delta-sigma ADC with scalable sampling rates and excess loop delay compensation

A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Multi-mode discrete-time delta-sigma modulator power optimization using split-integrator scheme

In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Excess loop delay compensation (ELC) for an analog to digital converter (ADC)

A controller enables the integration of a DC-DC converter in a mobile handset. The controller includes an input conditioner and an event sensor. The input conditioner uses a peak detector to track the output of a regulator and responds to available baseband input signals. The event sensor directs coupling between a voltage source and the DC-DC converter in response to a bypass event.

Devices and method for using a DC-DC converter in a mobile handset

A controller enables the integration of a DC-DC converter in an amplitude modulation power control loop in a mobile handset. The controller includes an input conditioner and an event sensor. The input conditioner uses a peak detector to track the output of a regulator and responds to available baseband input signals. The event sensor controls a switch that connects the DC-DC converter to a battery in response to a bypass event. The controller bypasses the DC-DC-converter when a transmitter is not enabled. The DC-DC converter is enabled prior to a transmission burst. A target voltage is determined from a series of detected peak voltages from the output of the regulator. The controller commands the DC-DC converter to transition to the target voltage until the end of a transmission burst.

Controller and method for using a DC-DC converter in a mobile handset

A voltage converter having a controller capable of maintaining stable operation of a voltage converter over multiple modes of operation. The voltage converter provides a feedback signal to an error signal generator. One or more controllers, which are selectively established as part of the feedback loop, process the error signal to generate a voltage converter charging cycle control signal. A pulse width modulator may be utilized to generate a voltage converter switch control signal that controls the charge cycle. A detector or comparator monitors one or more aspects of operation of the control circuit or the voltage converter to detect changes in the mode of operation. Upon detection of a change, the detector or comparator generate a multi-mode control signal to selectively switch one or more sub-controllers into or out of the feedback loop to thereby maintain desired stability, loop bandwidth, and response time.

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Aliso Viejo, CA, United States of America

Elias Dagher