Azul Systems, Inc.

Schlumberger Technologies, Inc.

Elias Atmeh

Scott D Sellers

Jack H Choquette

Kevin B Normoyle

Murali Sundaresan

Manuel Olivier Gautho

Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.

Multi-level power monitoring, filtering and throttling at local blocks and globally

A die with embedded memory is packaged together in a same dual-chip package with an EEPROM die. Defects in the embedded memory can be repaired using redundant rows or columns. A built-in self-test (BIST) controller locates defects and a repair image is generated. The repair image is stored in non-volatile memory in the EEPROM die. At power-up, the repair image is copied from the EEPROM die to a volatile repair RAM in the embedded memory die. The redundant rows or columns are mapped to replace defective rows/columns using the repair image in the volatile repair RAM. Although the embedded-memory die has only volatile memory and no fuses, its embedded memory can be repaired using the repair map from the non-volatile EEPROM die. Since the EEPROM die is in the same dual-chip package as the embedded memory die, the repair map is always available.

Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information

A packet generator that increases the output speed of column and row addresses and data provided by a semiconductor device test system. The packet generator receives column and row addresses and data from a conventional algorithmic pattern generator (APG) and generates column and row addresses and data in packet form, thereby allowing communications with a packet-based device under test, such as a memory. The packet generator further provides variable time spacing between column and row addresses and data packets. Thereby, the packet generator advantageously allows testing of memory devices that require signal inputs at a higher rate than a conventional APG can provide.

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San Jose, CA, United States of America

Elias Atmeh